公开(公告)号：US20240096424A1

公开(公告)日：2024-03-21

申请号：US18306654

申请日：2023-04-25

Applicant: Kioxia Corporation

Inventor： Takuya FUTATSUYAMA ,  Kenichi ABE

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B41/27 ,  H10B41/35

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H10B41/27 ,  H10B41/35

Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.

公开(公告)号：US20230317173A1

公开(公告)日：2023-10-05

申请号：US18326587

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC: G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C11/5635 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/3445

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US20230186994A1

公开(公告)日：2023-06-15

申请号：US18167133

申请日：2023-02-10

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA

IPC: G11C16/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C11/5671 ,  G11C16/3459 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

公开(公告)号：US20220148657A1

公开(公告)日：2022-05-12

申请号：US17585370

申请日：2022-01-26

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US20230168808A1

公开(公告)日：2023-06-01

申请号：US18101338

申请日：2023-01-25

Applicant: Kioxia Corporation

Inventor： Takuya FUTATSUYAMA

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

CPC classification number: G06F3/061 ,  G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/0408 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0688 ,  G11C16/045 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/3418

Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

公开(公告)号：US20220005533A1

公开(公告)日：2022-01-06

申请号：US17476279

申请日：2021-09-15

Applicant: KIOXIA CORPORATION

Inventor： Takuya FUTATSUYAMA ,  Kenichi ABE

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11524 ,  G11C16/04

Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.