公开(公告)号：US20060214218A1

公开(公告)日：2006-09-28

申请号：US11258823

申请日：2005-10-25

申请人： Kiyokazu Shishido ,  Masahiko Higashi ,  Minh Ngo ,  Angela Hui ,  Wenmei Li ,  Ning Cheng ,  Mark Ramsbey ,  Hirokazu Tokuno ,  Pei-Yuan Gao ,  Takayuki Enda

发明人： Kiyokazu Shishido ,  Masahiko Higashi ,  Minh Ngo ,  Angela Hui ,  Wenmei Li ,  Ning Cheng ,  Mark Ramsbey ,  Hirokazu Tokuno ,  Pei-Yuan Gao ,  Takayuki Enda

IPC分类号： H01L29/792

CPC分类号： H01L21/76801 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/3144 ,  H01L21/31625 ,  H01L21/76829 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/513

摘要： A semiconductor device includes a semiconductor substrate, an ONO film that is provided on the semiconductor substrate and has a contact hole, and an interlayer insulating film that is provided directly on the ONO film and contains phosphorus. The interlayer insulating film contains 4.5 wt % of phosphorus or more in an interface portion that interfaces with the ONO film. The interlayer insulating film comprises a first portion that contacts the ONO film, and a second portion provided on the first portion. The first portion has a phosphorus concentration more than that of the second portion.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底上并具有接触孔的ONO膜，以及直接设置在ONO膜上并含有磷的层间绝缘膜。 在与ONO膜接合的界面部分中，层间绝缘膜含有4.5重量％以上的磷。 层间绝缘膜包括接触ONO膜的第一部分和设置在第一部分上的第二部分。 第一部分的磷浓度大于第二部分的磷浓度。

公开(公告)号：US20050006693A1

公开(公告)日：2005-01-13

申请号：US10617450

申请日：2003-07-11

申请人： Minh Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yang ,  Robert Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yang ,  Robert Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。

公开(公告)号：US07300886B1

公开(公告)日：2007-11-27

申请号：US11147208

申请日：2005-06-08

申请人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

IPC分类号： H01L21/31

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

摘要翻译： 一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。 该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。 该方法还包括在高温下在控制栅极上沉积层间电介质。

公开(公告)号：US07023046B2

公开(公告)日：2006-04-04

申请号：US10617450

申请日：2003-07-11

申请人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。

公开(公告)号：US07297592B1

公开(公告)日：2007-11-20

申请号：US11195201

申请日：2005-08-01

申请人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn Hopper ,  Pei-Yuan Gao

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L21/3185 ,  H01L27/11568

摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

摘要翻译： 一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。 层间绝缘层沉积在数据保持衬里上。

公开(公告)号：US06803313B2

公开(公告)日：2004-10-12

申请号：US10256368

申请日：2002-09-27

申请人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

发明人： Pei-Yuan Gao ,  Lu You ,  Richard J. Huang

IPC分类号： H01L2144

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

摘要翻译： 双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。 通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。 结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。 这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

公开(公告)号：US06653735B1

公开(公告)日：2003-11-25

申请号：US10209447

申请日：2002-07-30

申请人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

发明人： Chih Yuh Yang ,  Douglas Bonser ,  Pei-Yuan Gao ,  Lu You

IPC分类号： H01L2348

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/32139

摘要： A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

摘要翻译： 使用包含具有比氮氧化硅更小的针孔密度的材料的BARC和具有比非晶碳更接近于多晶硅热膨胀系数的热膨胀系数的材料来减少将形成的图案的变形 可图案层。 可图案层形成在衬底上。 在可图案层上形成多层抗反射涂层。 在涂层上形成光致抗蚀剂图案。 涂层可以包括在可图案层上形成的无定形碳层和具有比在无定形碳层上形成的SiON的针孔密度小的针孔密度的SiC层。 涂层也可以形成在多晶硅层上，并且包括热膨胀缓冲层，其热膨胀系数比无定形碳的热膨胀系数更接近于多晶硅的热膨胀系数。

公开(公告)号：US20090176369A1

公开(公告)日：2009-07-09

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Eric Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Eric Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US06803265B1

公开(公告)日：2004-10-12

申请号：US10109234

申请日：2002-03-27

申请人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn M. Hopper ,  Pei-Yuan Gao

发明人： Minh Van Ngo ,  Arvind Halliyal ,  Tazrien Kamal ,  Hidehiko Shiraiwa ,  Rinji Sugino ,  Dawn M. Hopper ,  Pei-Yuan Gao

IPC分类号： H01L21337

CPC分类号： H01L27/11568 ,  H01L23/26 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.

摘要翻译： 集成电路存储器的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 减少的氢，紫外阻挡数据保持衬里覆盖字线和电荷捕获介电层。 与现有技术相比，降低的氢含量降低了电荷损失。 在完成集成电路之前，衬里的表面被处理以阻挡UV光。

公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.