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13 条记录 (耗时 0.051 秒)

    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
    2.
    发明申请
    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
    使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻

    公开(公告)号：US20070029604A1

    公开(公告)日：2007-02-08

    申请号：US11546688

    申请日：2006-10-12

    申请人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

    发明人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

    摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。

    Low stress sidewall spacer in integrated circuit technology
    7.
    发明申请
    Low stress sidewall spacer in integrated circuit technology 有权
    集成电路技术中的低应力侧壁间隔

    公开(公告)号：US20050153496A1

    公开(公告)日：2005-07-14

    申请号：US10756023

    申请日：2004-01-12

    申请人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

    发明人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

    IPC分类号： H01L21/336 ,  H01L21/4763

    CPC分类号： H01L29/6659 ,  H01L29/665

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

    Tensile strained substrate
    8.
    发明申请
    Tensile strained substrate 有权
    拉伸应变基材

    公开(公告)号：US20060138479A1

    公开(公告)日：2006-06-29

    申请号：US11356606

    申请日：2006-02-17

    申请人： Minh Ngo ,  Paul Besser ,  Ming Lin ,  Haihong Wang

    发明人： Minh Ngo ,  Paul Besser ,  Ming Lin ,  Haihong Wang

    IPC分类号： H01L29/76 ,  H01L23/58

    CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Ultra-uniform silicides in integrated circuit technology
    9.
    发明申请
    Ultra-uniform silicides in integrated circuit technology 有权
    集成电路技术中超均匀的硅化物

    公开(公告)号：US20050006705A1

    公开(公告)日：2005-01-13

    申请号：US10615086

    申请日：2003-07-07

    申请人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

    发明人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062

    CPC分类号： H01L21/28518

    摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

    摘要翻译： 提供一种集成电路的形成方法和结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

    System and method for processing an organic memory cell
    10.
    发明申请
    System and method for processing an organic memory cell 有权
    用于处理有机存储单元的系统和方法

    公开(公告)号：US20070090343A1

    公开(公告)日：2007-04-26

    申请号：US11256558

    申请日：2005-10-21

    申请人： Nicolay Yudanov ,  Igor Sokolik ,  Richard Kingsborough ,  William Leonard ,  Suzette Pangrle ,  Nicholas Tripsas ,  Minh Ngo

    发明人： Nicolay Yudanov ,  Igor Sokolik ,  Richard Kingsborough ,  William Leonard ,  Suzette Pangrle ,  Nicholas Tripsas ,  Minh Ngo

    IPC分类号： H01L29/08

    CPC分类号： H01L51/001 ,  C23C16/54 ,  H01J2237/3321 ,  H01L27/285

    摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

    摘要翻译： 公开了一种用于处理有机存储单元的系统和方法。 示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。 晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。 钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。 结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。 该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。