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公开(公告)号：US20070148895A1
公开(公告)日：2007-06-28
申请号：US11319075
申请日：2005-12-28
IPC分类号： H01L21/00
CPC分类号： H01G5/18 , H01F17/0006 , H01F17/02 , H01F21/04 , H01F27/40 , H01F41/041 , H01L28/10 , H01L28/40
摘要： Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor.
摘要翻译： 描述了在衬底上整体形成高Q可调谐电容器和高Q电感器的方法。 用于在基板上一体地形成电容器和微线圈的方法可以包括在基板上沉积和图案化电介质层，在衬底上沉积和图案化牺牲层，在半导体衬底上沉积和图案化导电材料，沉积和图案化聚合物 去除由所述图案化聚合物层暴露的所述导电材料的暴露部分，以从所述半导体衬底释放所述导电图案的一部分，以形成所述微线圈的面外绕组，将第二导电材料沉积在暴露的 部分导电材料，并去除牺牲层。 图案化导电材料可以包括微线圈的绕组部分，电容器的重叠电极部分和用于电容器电极的支撑部分。
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公开(公告)号：US07517769B2
公开(公告)日：2009-04-14
申请号：US11319075
申请日：2005-12-28
IPC分类号： H01L21/20
CPC分类号： H01G5/18 , H01F17/0006 , H01F17/02 , H01F21/04 , H01F27/40 , H01F41/041 , H01L28/10 , H01L28/40
摘要： Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor.
摘要翻译： 描述了在衬底上整体形成高Q可调谐电容器和高Q电感器的方法。 用于在基板上一体地形成电容器和微线圈的方法可以包括在基板上沉积和图案化电介质层，在衬底上沉积和图案化牺牲层，在半导体衬底上沉积和图案化导电材料，沉积和图案化聚合物 去除由所述图案化聚合物层暴露的所述导电材料的暴露部分，以从所述半导体衬底释放所述导电图案的一部分，以形成所述微线圈的面外绕组，将第二导电材料沉积在暴露的 部分导电材料，并去除牺牲层。 图案化导电材料可以包括微线圈的绕组部分，电容器的重叠电极部分和用于电容器电极的支撑部分。
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3.发明申请公开(公告)号：US20070145523A1
公开(公告)日：2007-06-28
申请号：US11319056
申请日：2005-12-28
申请人： Eugene Chow , Koenraad Schuylenbergh , David Fork , JengPing Lu
发明人： Eugene Chow , Koenraad Schuylenbergh , David Fork , JengPing Lu
IPC分类号： H01L29/00
CPC分类号： H01G5/18 , B81B3/0051 , H01F17/0006 , H01F17/02 , H01F21/04 , H01F27/40 , H01L28/10 , H01L28/60
摘要： Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom electrode structure to removing a suspension portion of a moveable top electrode from an RF part of a circuit.
摘要翻译： 描述了在衬底上整体形成高Q可调电容器和高Q电感器的方法。 可变电容器可以在可移动电极和固定电极之间使用停止以减少和/或防止可移动和固定电极之间的电短路。 电容器可以采用分离的底部电极结构来从电路的RF部分去除可移动顶部电极的悬挂部分。
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公开(公告)号：US06658728B2
公开(公告)日：2003-12-09
申请号：US09917572
申请日：2001-07-27
IPC分类号： H05K330
CPC分类号： G01R1/06716 , B81B2203/0118 , B81C1/00484 , B81C2201/0136 , B81C2203/058 , G01R1/06727 , G01R1/07342 , G01R3/00 , H01L23/49811 , H01L2924/0002 , H01R4/48 , H01R12/57 , H05K3/4092 , Y10T29/4913 , Y10T29/49135 , Y10T29/4914 , H01L2924/00
摘要： Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.
摘要翻译： 通过使用单个掩模通过形成弹簧金属和释放材料层来将含有接触垫或金属通孔的弹性结构光刻制造到衬底上的有效方法。 具体地说，使用光致抗蚀剂掩模或电镀金属图案或使用剥离处理技术，释放材料垫与弹簧金属手指自对准。 然后使用释放掩模释放弹簧金属指，同时保持将弹簧金属指的锚固部分固定到基底的释放材料的一部分。 当释放材料是导电的（例如钛）时，该释放材料部分直接位于接触垫或金属通孔上方，并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时，形成金属带以将弹簧金属手指连接到接触垫/通孔。
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公开(公告)号：US06361331B1
公开(公告)日：2002-03-26
申请号：US09923600
申请日：2001-08-06
IPC分类号： H01R909
摘要： Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad or metal via, and also to further anchor the spring metal finger to the substrate.
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公开(公告)号：US09961771B2
公开(公告)日：2018-05-01
申请号：US13571252
申请日：2012-08-09
申请人： JengPing Lu , Eugene M. Chow
发明人： JengPing Lu , Eugene M. Chow
CPC分类号： H05K1/142 , H05K1/0286 , H05K1/14 , H05K3/368 , H05K2201/09963 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern.
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7.发明授权Systems and methods for biasing high fill-factor sensor arrays and the like 有权用于偏置高填充因子传感器阵列等的系统和方法公开(公告)号：US07863703B2
公开(公告)日：2011-01-04
申请号：US12379581
申请日：2009-02-25
发明人： JengPing Lu , James B. Boyce
IPC分类号： H01L29/868 , H01L31/105
CPC分类号： H01L27/1446 , H01L31/105
摘要： A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.
摘要翻译： 形成高填充因子光电传感器阵列，其包括P层，I层，与I层相邻并且各自耦合到N层的一个或多个半导体结构，形成在P的顶部上的导电电极 以及与N层相邻并且与电压偏置源电连接的附加半导体结构。 施加到附加半导体结构的偏置电压对附加的半导体结构进行充电，从而在N层和P层之间产生隧穿效应，其中电子离开N层并到达P层和导电层。 电子然后在整个导电层中均匀迁移和均匀分布，这确保跨越整个光电传感器阵列的均匀偏压。 本发明的偏置方案允许在不使用引线接合的情况下实现光电传感器的批量生产。
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8.发明申请Systems and methods for biasing high fill-factor sensor arrays and the like 有权用于偏置高填充因子传感器阵列等的系统和方法公开(公告)号：US20090160006A1
公开(公告)日：2009-06-25
申请号：US12379581
申请日：2009-02-25
申请人： JengPing Lu , James B. Boyce , Kathleen Dore Boyce
发明人： JengPing Lu , James B. Boyce , Kathleen Dore Boyce
IPC分类号： H01L31/105 , H03K3/01
CPC分类号： H01L27/1446 , H01L31/105
摘要： A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.
摘要翻译： 形成高填充因子光电传感器阵列，其包括P层，I层，与I层相邻并且各自耦合到N层的一个或多个半导体结构，形成在P的顶部上的导电电极 以及与N层相邻并且与电压偏置源电连接的附加半导体结构。 施加到附加半导体结构的偏置电压对附加的半导体结构进行充电，从而在N层和P层之间产生隧穿效应，其中电子离开N层并到达P层和导电层。 电子然后在整个导电层中均匀迁移和均匀分布，这确保跨越整个光电传感器阵列的均匀偏压。 本发明的偏置方案允许在不使用引线接合的情况下实现光电传感器的批量生产。
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9.发明申请公开(公告)号：US20080141877A1
公开(公告)日：2008-06-19
申请号：US11613159
申请日：2006-12-19
IPC分类号： B41M1/10
CPC分类号： B41M1/10 , B41M1/04 , B41M1/06 , H05K3/207 , H05K2201/091 , H05K2203/105
摘要： A printing surface includes a substrate having latching electrodes on a first surface, a spacer layer on the first surface of the substrate, the spacer layer patterned to form wells such that the latching electrodes reside in the wells, a deformable membrane, the membrane having conductive regions, on the spacer layer to enclose the wells, each enclosed well and its associated region of the membrane forming a pixel membrane, and actuation circuitry to actuate the electrodes to cause selected ones of the pixel membranes to remain in a deflected state when the pixel membranes receive an impulse to return to an undeflected state.
摘要翻译： 打印表面包括在第一表面上具有锁定电极的基板，在基板的第一表面上的间隔层，图案化的间隔层以形成孔，使得锁定电极驻留在孔中，可变形的膜，该膜具有导电 区域，在间隔层上包围孔，每个封闭的井及其膜的相关区域形成像素膜，以及致动电路，用于致动电极，以使像素膜中选定的像素膜保持在偏转状态，当像素 膜受到冲击以返回到未偏转的状态。
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公开(公告)号：US08283566B2
公开(公告)日：2012-10-09
申请号：US12404294
申请日：2009-03-14
申请人： JengPing Lu , Eugene M. Chow
发明人： JengPing Lu , Eugene M. Chow
IPC分类号： H05K1/00
CPC分类号： H05K1/142 , H05K1/0286 , H05K1/14 , H05K3/368 , H05K2201/09963 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern. A circuit substrate, has a desired circuit pattern on a substrate, the substrate made up of at least two unit cells having conductive lines electrically connected together.
摘要翻译： 形成互连衬底的方法包括提供至少两个单元电池，布置单元电池以形成期望的电路图案，以及连接单元电池以形成具有所需电路图案的互连衬底。 电路基板在基板上具有期望的电路图案，该基板由具有电连接在一起的导电线的至少两个单电池构成。
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