Method of manufacturing hetero-junction bipolar transistor
    1.
    发明授权
    Method of manufacturing hetero-junction bipolar transistor 失效
    异质结双极晶体管的制造方法

    公开(公告)号:US06455390B2

    公开(公告)日:2002-09-24

    申请号:US09861614

    申请日:2001-05-22

    IPC分类号: H01L21331

    CPC分类号: H01L29/66318

    摘要: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

    摘要翻译: 一种制造包含碳掺杂基底层的异质结双极晶体管的方法包括以下步骤:(a)通过化学气相沉积在下层生长基底层,(b)在基底层上形成至少一个半导体层 ,(c)然后在520℃至650℃的温度下对基层进行热退火。

    Method of manufacturing hetero-junction bipolar transistor
    2.
    发明授权
    Method of manufacturing hetero-junction bipolar transistor 失效
    异质结双极晶体管的制造方法

    公开(公告)号:US06258685B1

    公开(公告)日:2001-07-10

    申请号:US09376299

    申请日:1999-08-18

    IPC分类号: H01L21331

    CPC分类号: H01L29/66318

    摘要: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

    摘要翻译: 一种制造包含碳掺杂基底层的异质结双极晶体管的方法包括以下步骤:(a)通过化学气相沉积在下层生长基底层,(b)在基底层上形成至少一个半导体层 ,(c)然后在520℃至650℃的温度下对基层进行热退火。

    Semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号:US08786092B2

    公开(公告)日:2014-07-22

    申请号:US13240054

    申请日:2011-09-22

    IPC分类号: H01L23/50

    摘要: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

    摘要翻译: 半导体集成电路器件包括:矩形半导体衬底; 形成在所述半导体衬底上或之上的金属布线层; 以及覆盖金属布线层的钝化层。 在半导体基板的角部设置没有形成金属布线层的部分的角部非布线区域。 在金属布线层的靠近半导体基板的角部的部分形成狭缝。 钝化层包括形成在金属布线层上的第一钝化层和形成在第一钝化层上的第二钝化层。 第一钝化层由比第二钝化层的材料软的材料形成。

    Nut, female thread machining device and female thread machining method
    7.
    发明授权
    Nut, female thread machining device and female thread machining method 有权
    螺母,内螺纹加工装置和内螺纹加工方法

    公开(公告)号:US08419556B2

    公开(公告)日:2013-04-16

    申请号:US12547001

    申请日:2009-08-25

    IPC分类号: B21D53/24 B21H3/08 B21K1/64

    摘要: There is provided a nut having a thread portion having a female thread, a metallic plate portion having a base segment, and a hardness gradient portion provided between the thread portion and the metallic plate portion. The thread portion, metallic plate portion and the hardness gradient portion are monolithic each other, a metallographic structure of the metallic plate portion differs from a metallographic structure of the thread portion and a hardness of the hardness gradient portion is lower than a hardness of the thread portion and lowers from the thread portion toward the metallic plate portion.

    摘要翻译: 提供一种具有内螺纹的螺纹部分的螺母,具有基部段的金属板部分和设置在螺纹部分和金属板部分之间的硬度梯度部分。 螺纹部分,金属板部分和硬度梯度部分是彼此整体的,金属板部分的金相组织与螺纹部分的金相组织不同,硬度梯度部分的硬度低于螺纹的硬度 从螺纹部分向金属板部分下降。