公开(公告)号：US20110080766A1

公开(公告)日：2011-04-07

申请号：US12574938

申请日：2009-10-07

Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

IPC: H01L45/00 ,  H01L21/28 ,  G11C11/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

公开(公告)号：US08675381B2

公开(公告)日：2014-03-18

申请号：US12839842

申请日：2010-07-20

Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

IPC: G11C5/06

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

公开(公告)号：US08501574B2

公开(公告)日：2013-08-06

申请号：US12574938

申请日：2009-10-07

Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

IPC: H01L21/20

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

公开(公告)号：US08284597B2

公开(公告)日：2012-10-09

申请号：US12904792

申请日：2010-10-14

Applicant: Kuo-Pin Chang ,  Hang-Ting Lue

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C11/36

CPC classification number: G11C13/0002 ,  G11C2213/33 ,  G11C2213/72

Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Abstract translation: 二极管存储器件在两个端子之间具有中间结构，例如p端子和n端子。

公开(公告)号：US20120020138A1

公开(公告)日：2012-01-26

申请号：US12839842

申请日：2010-07-20

Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

IPC: G11C5/06

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

公开(公告)号：US20110273930A1

公开(公告)日：2011-11-10

申请号：US12904792

申请日：2010-10-14

Applicant: Kuo-Pin Chang ,  Hang-Ting Lue

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C11/36

CPC classification number: G11C13/0002 ,  G11C2213/33 ,  G11C2213/72

Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Abstract translation: 二极管存储器件在两个端子之间具有中间结构，例如p端子和n端子。

公开(公告)号：US08987098B2

公开(公告)日：2015-03-24

申请号：US13527259

申请日：2012-06-19

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L21/336 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11565

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US08889509B2

公开(公告)日：2014-11-18

申请号：US13210202

申请日：2011-08-15

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L21/336 ,  H01L29/792 ,  H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract translation: 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC: H01L29/788

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

Abstract: An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

Abstract translation: 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20130175598A1

公开(公告)日：2013-07-11

申请号：US13347331

申请日：2012-01-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/792 ,  H01L21/8239

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。