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    Transistor having an adjustable gate resistance and semiconductor device comprising the same
    1.
    发明授权
    Transistor having an adjustable gate resistance and semiconductor device comprising the same 有权
    具有可调节栅极电阻的晶体管和包括其的半导体器件

    公开(公告)号：US08675381B2

    公开(公告)日：2014-03-18

    申请号：US12839842

    申请日：2010-07-20

    Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

    Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

    IPC: G11C5/06

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

    Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

    Resistive Memory Device and Manufacturing Method Thereof and Operating Method Thereof
    2.
    发明申请
    Resistive Memory Device and Manufacturing Method Thereof and Operating Method Thereof 有权
    电阻式存储器件及其制造方法及其操作方法

    公开(公告)号：US20110080766A1

    公开(公告)日：2011-04-07

    申请号：US12574938

    申请日：2009-10-07

    Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    IPC: H01L45/00 ,  H01L21/28 ,  G11C11/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

    Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

    Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

    Resistive memory device and manufacturing method thereof and operating method thereof
    3.
    发明授权
    Resistive memory device and manufacturing method thereof and operating method thereof 有权
    电阻式存储器件及其制造方法及其操作方法

    公开(公告)号：US08501574B2

    公开(公告)日：2013-08-06

    申请号：US12574938

    申请日：2009-10-07

    Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    IPC: H01L21/20

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

    Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

    Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

    TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
    5.
    发明申请
    TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME 有权
    具有可调节栅极电阻的晶体管和包含该栅极电阻的半导体器件

    公开(公告)号：US20120020138A1

    公开(公告)日：2012-01-26

    申请号：US12839842

    申请日：2010-07-20

    Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

    Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

    IPC: G11C5/06

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

    Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

    Memory and Method of Fabricating the Same
    7.
    发明申请
    Memory and Method of Fabricating the Same 有权
    内存及其制作方法

    公开(公告)号：US20110089393A1

    公开(公告)日：2011-04-21

    申请号：US12581219

    申请日：2009-10-19

    Applicant: Kuo-Pin Chang ,  Erh-Kun Lai

    Inventor： Kuo-Pin Chang ,  Erh-Kun Lai

    IPC: H01L45/00 ,  H01L29/12 ,  H01L21/34

    CPC classification number: G11C11/5685 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal element, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

    Abstract translation: 提供了包括金属部分，第一金属层和第二金属氧化物层的存储器。 第一金属氧化物层在金属元件上，第一金属氧化物层包括N电阻水平。 第二金属氧化物层在第一金属氧化物层上，第二金属氧化物层包括M电阻水平。 存储器具有X电阻电平，并且X小于M和N的总和，以最小化编程干扰。

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