利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.034 秒)

    Method of forming semiconductor device
    3.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US08546256B2

    公开(公告)日：2013-10-01

    申请号：US13167225

    申请日：2011-06-23

    申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

    摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20110318922A1

    公开(公告)日：2011-12-29

    申请号：US13167225

    申请日：2011-06-23

    申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

    摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

    摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE 有权
    集成电路设备，通过具有偏移接口的结构，包括硅

    公开(公告)号：US20130119547A1

    公开(公告)日：2013-05-16

    申请号：US13603978

    申请日：2012-09-05

    申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    IPC分类号： H01L23/532 ,  H01L23/498

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

    摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

    摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

    Semiconductor device and method of fabricating the same
    8.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07518214B2

    公开(公告)日：2009-04-14

    申请号：US11586610

    申请日：2006-10-26

    申请人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

    发明人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

    IPC分类号： H01L29/00

    CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

    摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

    摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。