公开(公告)号：US20130119547A1

公开(公告)日：2013-05-16

申请号：US13603978

申请日：2012-09-05

申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

IPC分类号： H01L23/532 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

公开(公告)号：US08884440B2

公开(公告)日：2014-11-11

申请号：US13603978

申请日：2012-09-05

申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-lyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-lyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

公开(公告)号：US09530726B2

公开(公告)日：2016-12-27

申请号：US14052691

申请日：2013-10-11

申请人： Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

发明人： Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

摘要翻译： 半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线 结构体。

公开(公告)号：US20140035164A1

公开(公告)日：2014-02-06

申请号：US14052691

申请日：2013-10-11

申请人： Kwang-jin Moon ,  Byung-lyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

发明人： Kwang-jin Moon ,  Byung-lyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

IPC分类号： H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

摘要翻译： 半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线 结构体。

公开(公告)号：US08546256B2

公开(公告)日：2013-10-01

申请号：US13167225

申请日：2011-06-23

申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

IPC分类号： H01L21/283

CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

公开(公告)号：US09018768B2

公开(公告)日：2015-04-28

申请号：US13627790

申请日：2012-09-26

申请人： Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

发明人： Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

摘要： A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

摘要翻译： 半导体器件包括在衬底的第一表面上的电路图案，覆盖电路图案的绝缘夹层，填充通过绝缘夹层和衬底的通孔的TSV结构，在通孔的内壁上的绝缘层结构 并且在绝缘中间层的上表面上，具有TSV结构和绝缘层结构的缓冲层，通过绝缘层结构的导电结构和电连接到电路图案的绝缘夹层的一部分，接触垫 到TSV结构的底部，以及在第二表面上的保护层结构，以包围接触垫。

公开(公告)号：US20110318922A1

公开(公告)日：2011-12-29

申请号：US13167225

申请日：2011-06-23

申请人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

发明人： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

IPC分类号： H01L21/283

CPC分类号： H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

摘要： The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

摘要翻译： 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。

公开(公告)号：US20140021633A1

公开(公告)日：2014-01-23

申请号：US13919580

申请日：2013-06-17

申请人： Do-Sun Lee ,  Kun-Sang Park ,  Byung-Lyul Park ,  Seong-min Son ,  Gil-heyun Choi

发明人： Do-Sun Lee ,  Kun-Sang Park ,  Byung-Lyul Park ,  Seong-min Son ,  Gil-heyun Choi

IPC分类号： H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.

摘要翻译： 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件及其制造方法。 集成电路器件可以包括穿透半导体结构的TSV结构。 TSV结构可以包括包括第一浓度的杂质的第一通过电极单元和包括大于第一浓度的第二浓度的杂质的第二通过电极单元。

公开(公告)号：US20100193902A1

公开(公告)日：2010-08-05

申请号：US12502490

申请日：2009-07-14

申请人： Seung-woo SHIN ,  Byung-Iyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

发明人： Seung-woo SHIN ,  Byung-Iyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

IPC分类号： H01L23/525

CPC分类号： H01L23/5258 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.

摘要翻译： 提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。 半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层， 除了保护层。

公开(公告)号：US20120052635A1

公开(公告)日：2012-03-01

申请号：US13221158

申请日：2011-08-30

申请人： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

发明人： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203

摘要： A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

摘要翻译： 公开了一种导电层掩埋型衬底。 基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上 并且包括金属层和形成在导电层上的单晶半导体层。