利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

102 条记录 (耗时 0.039 秒)

    Method for plating printed circuit board and printed circuit board manufactured therefrom
    1.
    发明申请
    Method for plating printed circuit board and printed circuit board manufactured therefrom 审中-公开
    电镀印刷电路板和印刷电路板的方法

    公开(公告)号：US20070104929A1

    公开(公告)日：2007-05-10

    申请号：US11586006

    申请日：2006-10-25

    申请人： Kyu Yim ,  Sung Chun ,  Dek Yang ,  Dong An ,  Chul Lee ,  Mi Han

    发明人： Kyu Yim ,  Sung Chun ,  Dek Yang ,  Dong An ,  Chul Lee ,  Mi Han

    IPC分类号： B05D5/12 ,  B32B3/00

    CPC分类号： H05K3/244 ,  C23C18/44 ,  C23C18/54 ,  H01L21/4846 ,  H01L23/498 ,  H01L24/85 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/0002 ,  H05K3/28 ,  H05K2203/072 ,  H05K2203/073 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/01033

    摘要： Disclosed herein are a method for plating a printed circuit board and the printed circuit board manufactured therefrom. In the method, a bare soldering or wire bonding portion of a copper (Cu)- or copper alloy layer, is plated with palladium (Pd) or a palladium alloy, and then gold (Au) or a gold alloy is deposited over the palladium or palladium alloy plated layer by an electroless substitution plating process based on ionization tendency. Having superior hardness, ductility and corrosion resistance, palladium is suitable for use between a connector and a substrate and meets requirements for the printed circuit board even when applied to a low thickness, greatly reducing the process time. Accordingly, the problem of black pad, which frequently occur on electroless nickel and electroless gold finish upon surface mount technology, can be perfectly solved. Particularly, fatal bending cracks can be prevented from occurring in the rigid-flexible or flexible printed circuit boards.

    摘要翻译： 这里公开了印刷电路板和由其制造的印刷电路板的电镀方法。 在该方法中，铜（Cu）或铜合金层的裸焊或引线接合部分镀钯（Pd）或钯合金，然后将金（Au）或金合金沉积在钯 或钯合金镀层，通过基于电离倾向的无电取代电镀工艺。 具有优异的硬度，延展性和耐腐蚀性，钯适用于连接器和基板之间，并且即使应用于低厚度也可满足印刷电路板的要求，大大减少了处理时间。 因此，通过表面贴装技术在化学镀镍和无电镀金上经常出现的黑色焊盘的问题可以得到很好的解决。 特别地，可以防止在刚性柔性或柔性印刷电路板中发生致命的弯曲裂纹。

    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION
    2.
    发明公开
    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION 审中-公开

    公开(公告)号：US20230230671A1

    公开(公告)日：2023-07-20

    申请号：US17992424

    申请日：2022-11-22

    申请人： Chul Lee ,  Hesamoddin Salehian

    发明人： Chul Lee ,  Hesamoddin Salehian

    IPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    CPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    摘要： A method for decreasing a number of individual entries in a database of user-created records which describe a single item by: receiving a plurality of user-created records, each of said records comprising at least a descriptive string; placing individual ones of the plurality of user-created records having a sufficiently similar descriptive string into one of a plurality of first groups; hashing the descriptive string of each of the plurality of first groups in order to place two or more groups into a single bin; performing a pair-wise comparison of the descriptive strings of the two or more groups in each bin; and when the comparison of the descriptive strings of the two or more groups in a bin results in a distance below a first threshold, merging the two or more groups into a combined group.

    Recessed transistor and method of manufacturing the same
    3.
    发明授权
    Recessed transistor and method of manufacturing the same 有权
    嵌入式晶体管及其制造方法

    公开(公告)号：US09012982B2

    公开(公告)日：2015-04-21

    申请号：US12068179

    申请日：2008-02-04

    申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

    摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

    Semiconductor Devices Including Transistors Having Three Dimensional Channels
    8.
    发明申请
    Semiconductor Devices Including Transistors Having Three Dimensional Channels 审中-公开
    包括具有三维通道的晶体管的半导体器件

    公开(公告)号：US20080315282A1

    公开(公告)日：2008-12-25

    申请号：US12199237

    申请日：2008-08-27

    申请人： Eun-Suk Cho ,  Chul Lee

    发明人： Eun-Suk Cho ,  Chul Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

    Fin field effect transistor device and method of fabricating the same
    9.
    发明授权
    Fin field effect transistor device and method of fabricating the same 失效
    Fin场效应晶体管器件及其制造方法

    公开(公告)号：US07323375B2

    公开(公告)日：2008-01-29

    申请号：US11091457

    申请日：2005-03-28

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

    摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

    摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
    10.
    发明授权
    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
    具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法

    公开(公告)号：US07227220B2

    公开(公告)日：2007-06-05

    申请号：US11240544

    申请日：2005-09-30

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。