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    Process of forming copper structures
    1.
    发明授权
    Process of forming copper structures 失效
    形成铜结构的工艺

    公开(公告)号：US06812143B2

    公开(公告)日：2004-11-02

    申请号：US10279057

    申请日：2002-10-24

    申请人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    发明人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    IPC分类号： H01L2144

    CPC分类号： H01L21/32051 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

    摘要翻译： 本发明的阻挡材料提供铜的电沉积。 阻挡层包括介电界面表面区域和具有至少50原子百分比的铜界面金属的铜界面表面区域。 特别地，本发明的阻挡层提供在直接电沉积工艺中将铜或铜合金直接电沉积在阻挡层的铜界面区域上。 该方法包括提供设置在底层上的电介质层，使阻挡层与电介质层接触，并将导电层沉积在阻挡层上。

    Stacked via-stud with improved reliability in copper metallurgy
    4.
    发明申请
    Stacked via-stud with improved reliability in copper metallurgy 审中-公开
    堆叠通孔，提高了铜冶金的可靠性

    公开(公告)号：US20060014376A1

    公开(公告)日：2006-01-19

    申请号：US11230841

    申请日：2005-09-20

    申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

    摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

    Metal capped copper interconnect
    8.
    发明授权
    Metal capped copper interconnect 有权
    金属封盖铜互连

    公开(公告)号：US07495338B2

    公开(公告)日：2009-02-24

    申请号：US11376199

    申请日：2006-03-16

    申请人： Michael Lane ,  Stefanie R. Chiras ,  Terry A. Spooner ,  Robert Rosenberg ,  Daniel C. Edelstein

    发明人： Michael Lane ,  Stefanie R. Chiras ,  Terry A. Spooner ,  Robert Rosenberg ,  Daniel C. Edelstein

    IPC分类号： H01L29/40

    CPC分类号： C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

    摘要翻译： 一种导电材料，包括：导电核心区域，其包含铜和0.001原子％至0.6原子％的选自铱，锇和铼的一种或多种金属; 和界面区域。 所述界面区域包含所述一种或多种金属的至少80原子％以上。 本发明还涉及一种制造导电材料的方法，包括：提供底层; 使底层与种子层接触，晶种层包含铜和一种或多种选自铱，锇和铼的金属; 在种子层上沉积包含铜的导电层，并且在足以在导电层中引起晶粒生长的温度下对导电层退火，同时最小化一种或多种合金金属从晶种层向导电层的迁移。 该方法还包括抛光导电层以提供抛光的铜表面材料，并且在一定温度下退火抛光的铜表面材料，以使一种或多种金属从晶种层迁移到抛光表面以提供接触的界面区域 具有铜导体核心区域。 界面区域和铜导体芯区域包括一种或多种金属。