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24 条记录 (耗时 0.017 秒)

    Control of liner thickness for improving thermal cycle reliability
    3.
    发明申请
    Control of liner thickness for improving thermal cycle reliability 失效
    控制衬套厚度，提高热循环的可靠性

    公开(公告)号：US20050227380A1

    公开(公告)日：2005-10-13

    申请号：US10815418

    申请日：2004-04-01

    申请人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

    IPC分类号： G06F13/28

    CPC分类号： G01R31/2881

    摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

    摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

    Deflection analysis system and method for circuit design
    6.
    发明申请
    Deflection analysis system and method for circuit design 失效
    偏转分析系统及电路设计方法

    公开(公告)号：US20070174796A1

    公开(公告)日：2007-07-26

    申请号：US11336524

    申请日：2006-01-20

    申请人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

    发明人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

    摘要翻译： 用于分析电路设计的系统，方法和计算机程序产品提供将电路设计离散成一系列像素。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。

    Process of forming copper structures
    7.
    发明授权
    Process of forming copper structures 失效
    形成铜结构的工艺

    公开(公告)号：US06812143B2

    公开(公告)日：2004-11-02

    申请号：US10279057

    申请日：2002-10-24

    申请人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    发明人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    IPC分类号： H01L2144

    CPC分类号： H01L21/32051 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

    摘要翻译： 本发明的阻挡材料提供铜的电沉积。 阻挡层包括介电界面表面区域和具有至少50原子百分比的铜界面金属的铜界面表面区域。 特别地，本发明的阻挡层提供在直接电沉积工艺中将铜或铜合金直接电沉积在阻挡层的铜界面区域上。 该方法包括提供设置在底层上的电介质层，使阻挡层与电介质层接触，并将导电层沉积在阻挡层上。

    MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT
    8.
    发明申请
    MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT 审中-公开
    通过可靠性增强的底部结构进行修改

    公开(公告)号：US20070281469A1

    公开(公告)日：2007-12-06

    申请号：US11839258

    申请日：2007-08-15

    申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

    摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

    Stacked via-stud with improved reliability in copper metallurgy
    10.
    发明申请
    Stacked via-stud with improved reliability in copper metallurgy 审中-公开
    堆叠通孔，提高了铜冶金的可靠性

    公开(公告)号：US20060014376A1

    公开(公告)日：2006-01-19

    申请号：US11230841

    申请日：2005-09-20

    申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

    摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。