公开(公告)号：US20130082764A1

公开(公告)日：2013-04-04

申请号：US13250677

申请日：2011-09-30

申请人： Paul Penzes ,  Love Kothari ,  Ajat Hukkoo ,  Mark Fullerton ,  Veronica Alarcon ,  Zhongmin Zhang ,  Kerry Alan Thompson ,  Russell Radke

发明人： Paul Penzes ,  Love Kothari ,  Ajat Hukkoo ,  Mark Fullerton ,  Veronica Alarcon ,  Zhongmin Zhang ,  Kerry Alan Thompson ,  Russell Radke

IPC分类号： G05F3/02 ,  H03B1/00 ,  G11C5/14

CPC分类号： G11C29/56 ,  G11C2029/5602

摘要： An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.

摘要翻译： 公开了一种在集成电路中组合焊盘功能的装置和方法。 电源，接地或信号焊盘分别连接到电源，接地或信号源。 电源，接地或信号焊盘另外连接到附加信号源，例如测试环境中的自动测试设备。 通过将电源，接地或信号源暂时断开与源传输到的集成电路内的功能块，同一焊盘可以将另一个信号传递到集成电路的其他部分。 在替代方案中，相同的焊盘可以将另一个信号传递到集成电路的其它部分，而不会通过在原始信号上耦合附加信号来断开原始信号。 此外，组合焊盘功能使得可以将输入焊盘重新用作来自集成电路内的信号作为输出焊盘。

公开(公告)号：US08954017B2

公开(公告)日：2015-02-10

申请号：US13247295

申请日：2011-09-28

申请人： Love Kothari ,  Ajat Hukkoo ,  Kerry Alan Thompson

发明人： Love Kothari ,  Ajat Hukkoo ,  Kerry Alan Thompson

IPC分类号： H04B1/40

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

摘要翻译： 公开了一种实现锁相环以将提供给电力管理单元（PMU）的时钟信号乘以可变整数值的通信设备。 乘以PMU时钟信号提供第二时钟信号，其中第二时钟信号的特征在于具有基本分量的一个或多个谐波的基波分量，该基波分量与基波分量和PMU时钟信号的一个或多个谐波不同。 具有第二时钟信号的一个或多个谐波的基波分量不占用与通信设备的发送通信信号相同的通信信道。 因此，最小化传输通信信号的劣化。

公开(公告)号：US09225343B2

公开(公告)日：2015-12-29

申请号：US13338001

申请日：2011-12-27

申请人： Love Kothari ,  Mark Fullerton ,  Rajesh Rajan ,  Veronica Alarcon

发明人： Love Kothari ,  Mark Fullerton ,  Rajesh Rajan ,  Veronica Alarcon

IPC分类号： H04L7/02 ,  H03L7/08 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  G06F12/14 ,  G06F21/44 ,  H03K5/13 ,  H03L7/097 ,  H03L7/099 ,  G06F1/32 ,  G06F1/26 ,  H03K5/00

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

摘要翻译： 公开了一种电子设备，其减少由基于快速时钟操作的第一电子元件与基于慢时钟操作的第二电子元件之间的通信而导致的延迟降低了通信延迟。 当将数据从第一分量传送到第二分量时，使用第一时钟将数据写入缓冲器，然后使用第二时钟由第二分量提取。 或者，当从第二组件传送数据到第一组件时，第一组件从第二组件读取数据并监视在第二时钟信号的相关边缘期间是否提取数据，在这种情况下，第一组件再次提取 来自第二个组件的数据。

公开(公告)号：US08745411B2

公开(公告)日：2014-06-03

申请号：US12614383

申请日：2009-11-06

申请人： Love Kothari ,  Lawrence J. Madar, III

发明人： Love Kothari ,  Lawrence J. Madar, III

IPC分类号： G06F21/00

CPC分类号： G06F12/1408 ,  G06F21/10 ,  G06F21/79 ,  G06F2221/2107 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/24 ,  Y02D10/13

摘要： A data processing apparatus includes a volatile memory, a random number generator adapted for generating random numbers from which one or more keys are generated, and a memory encryption unit (MEU). The MEU is configured to receive an N-bit block of data and to divide the N-bit block of data into two more sub-blocks of data, where each sub-block contains fewer than N-bits. The MEU is further configured to encrypt each sub-block of data using the one more keys, to combine the encrypted sub-blocks into an N-bit block of encrypted data, and to write the encrypted N-bit block of data to the volatile memory.

摘要翻译： 一种数据处理装置，包括易失性存储器，适于产生生成一个或多个密钥的随机数的随机数发生器和存储器加密单元（MEU）。 MEU被配置为接收N位数据块并且将N位数据块划分为两个更多的数据子块，其中每个子块包含少于N位。 MEU还被配置为使用一个以上的密钥来加密数据的每个子块，将加密的子块组合成N位的加密数据块，并将加密的N位数据块写入到易失性 记忆。

公开(公告)号：US08826039B2

公开(公告)日：2014-09-02

申请号：US12714383

申请日：2010-02-26

申请人： Paul Chou ,  Love Kothari ,  Lawrence J. Madar, III

发明人： Paul Chou ,  Love Kothari ,  Lawrence J. Madar, III

IPC分类号： G06F12/14

CPC分类号： G06F21/72 ,  G06F12/14

摘要： A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module.

摘要翻译： 一种提供硬件安全模块的技术，其提供用于将安全密钥保持在安全边界内的安全边界，并防止从安全边界外部的外部源的未经授权的访问以获得安全密钥。 硬件安全模块包括一个安全处理器，用于对安全边界内的安全密钥进行解包和认证，以对数据进行解密或加密，并通过与外部源通信的单一接口提供数据，从而在安全边界之间传输所有数据，由 硬件安全模块和外部源仅通过接口传输。 硬件安全模块确保没有解开的密钥离开硬件安全模块建立的安全边界。

公开(公告)号：US20130047000A1

公开(公告)日：2013-02-21

申请号：US13437675

申请日：2012-04-02

申请人： Veronica ALARCON ,  Love Kothari ,  Amar Guettaf ,  Kerry Thompson

发明人： Veronica ALARCON ,  Love Kothari ,  Amar Guettaf ,  Kerry Thompson

IPC分类号： G06F1/26

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit, Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

摘要翻译： 公开了一种集成电路，其包含PMU和诸如基带的另一处理部分。 由于PMU有限的引脚，PMU通过集成电路的其他处理部分接收大部分信号。因此，为了保护PMU，集成电路将PMU部分与其他信号接收不同的信号 直到满足某些条件之后。 此外，该集成电路包括另一个处理部分中的GPIO引脚组，该GPIO引脚组可以被自由地配置为允许对PMU进行测试。

公开(公告)号：US20110067110A1

公开(公告)日：2011-03-17

申请号：US12559154

申请日：2009-09-14

申请人： John Markey ,  Love Kothari ,  Paul Chou

发明人： John Markey ,  Love Kothari ,  Paul Chou

IPC分类号： G06F21/20 ,  G06F9/00

CPC分类号： G06F21/575 ,  G06F21/74 ,  G06F2221/2105

摘要： Aspects of a method and system for hardware enforced virtualization in an integrated circuit are provided. In this regard, a mode of operation of an integrated circuit may be controlled such that the integrated circuit alternates between a secure mode of operation and an open mode of operation. Various resources of the integrated circuit may be designated as open or secure, and secure resources may be made inaccessible while the integrated circuit operates in the open mode. Access to the secure resources may be controlled based on a configuration of one or more registers and/or switching elements. Resources designated as secure may comprise, for example, a one-time-programmable memory. The integrated circuit may comprise ROM and/or one-time-programmable memory that stores one or more instructions, wherein execution of the one or more instructions may control transitions between the secure mode and the open mode.

摘要翻译： 提供了集成电路中用于硬件强制虚拟化的方法和系统的方面。 在这方面，可以控制集成电路的操作模式，使得集成电路在安全操作模式和开放操作模式之间交替。 集成电路的各种资源可以被指定为开放的或安全的，并且当集成电路在开放模式下操作时，可以使安全的资源变得不可访问。 可以基于一个或多个寄存器和/或开关元件的配置来控制对安全资源的访问。 指定为安全的资源可以包括例如一次性可编程存储器。 集成电路可以包括存储一个或多个指令的ROM和/或一次可编程存储器，其中一个或多个指令的执行可以控制安全模式和打开模式之间的转换。

公开(公告)号：US20110066835A1

公开(公告)日：2011-03-17

申请号：US12559242

申请日：2009-09-14

申请人： Love Kothari ,  Paul Chou ,  John Markey

发明人： Love Kothari ,  Paul Chou ,  John Markey

IPC分类号： G06F15/177

CPC分类号： G06F21/33 ,  G06F11/3648

摘要： A semiconductor chip may be operable to block the debug interfaces when the semiconductor chip boots up from the boot read-only memory (ROM). The semiconductor chip may be operable to authenticate a debug certificate received by the semiconductor chip and enable one or more debug interfaces in the semiconductor chip based on the information resulting from the authentication of the debug certificate. The debug certificate may be in a form of a cryptographic public key certificate. A unique device ID which may be generated at boot and stored in the memory may be used by the semiconductor chip to authenticate the debug certificate. The device ID may be generated using the cryptographic public key that is stored in the one-time programmable (OTP) memory in the semiconductor chip and a cryptographic hash algorithm.

摘要翻译： 当半导体芯片从引导只读存储器（ROM）启动时，半导体芯片可以用于阻止调试接口。 半导体芯片可以用于对由半导体芯片接收到的调试证书进行认证，并且基于从调试证书的认证得到的信息来启用半导体芯片中的一个或多个调试接口。 调试证书可以是加密公钥证书的形式。 半导体芯片可以在启动时产生并存储在存储器中的独特的设备ID用于认证调试证书。 可以使用存储在半导体芯片中的一次可编程（OTP）存储器中的密码公钥和密码散列算法来生成设备ID。

公开(公告)号：US09407272B2

公开(公告)日：2016-08-02

申请号：US13341748

申请日：2011-12-30

申请人： Paul Penzes ,  Mark Fullerton ,  Hwisung Jung ,  John Walley ,  Tim Sippel ,  Love Kothari

发明人： Paul Penzes ,  Mark Fullerton ,  Hwisung Jung ,  John Walley ,  Tim Sippel ,  Love Kothari

IPC分类号： G06F9/46 ,  H03L7/08 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  G06F12/14 ,  G06F21/44 ,  H03K5/13 ,  H03L7/097 ,  H03L7/099 ,  G06F1/32 ,  G06F1/26 ,  H03K5/00

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

摘要翻译： 提出了系统和方法，以减少高负载和老化对处理器中处理器内核的影响。 电源管理单元（PMU）可以监视处理器内核的老化，温度和增加的负载。 PMU指示处理器采取行动，使得老化，温度和/或增加的负载大致均匀地分布在处理器核心上，使得处理器可以继续有效地处理指令。

公开(公告)号：US20130047272A1

公开(公告)日：2013-02-21

申请号：US13250529

申请日：2011-09-30

申请人： Love Kothari ,  Paul Chou

发明人： Love Kothari ,  Paul Chou

IPC分类号： G06F17/00

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： An integrated circuit is disclosed that can be included in a host electronic device that can be commonly manufactured, where the integrated circuit can be designated (“locked”) for a specific manufacturer, thereby substantially reducing the likelihood that a third party will be able to successfully clone a host electronic device manufactured by the specific manufacturer and/or swap the chip containing the integrated circuit for one having more enabled features. The integrated circuit includes an ID module that can be programmed after fabrication. Components within the integrated circuit designate manufacturer-specific configurations (e.g., address mapping, pin routing and/or vital function releasing) based on the programmed manufacturer ID. As a result, once the integrated circuit has been programmed with the manufacturer ID, the integrated circuit will function correctly only within a host device manufactured by the manufacturer associated with the programmed manufacturer ID.

摘要翻译： 公开了一种集成电路，其可以被包括在可以被共同制造的主机电子设备中，其中集成电路可以被指定（锁定）用于特定制造商，从而显着降低第三方将能够成功克隆的可能性 由特定制造商制造的主机电子设备和/或将包含集成电路的芯片交换为具有更多启用特征的芯片。 集成电路包括可在制造后编程的ID模块。 集成电路中的组件基于编程的制造商ID指定制造商特定的配置（例如，地址映射，引脚布线和/或重要功能释放）。 因此，一旦集成电路已经用制造商ID编程，集成电路将仅在制造商制造的与编程的制造商ID相关联的主机设备中正常工作。