HIGH MODULATION SPEED PIN-TYPE PHOTODIODE

    公开(公告)号:US20220246781A1

    公开(公告)日:2022-08-04

    申请号:US17249140

    申请日:2021-02-22

    Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

    High modulation speed PIN-type photodiode

    公开(公告)号:US12278304B2

    公开(公告)日:2025-04-15

    申请号:US17249140

    申请日:2021-02-22

    Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

    Fabrication of low-cost long wavelength VCSEL with optical confinement control

    公开(公告)号:US11611195B2

    公开(公告)日:2023-03-21

    申请号:US17138623

    申请日:2020-12-30

    Abstract: Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.

    FABRICATING SEMICONDUCTOR DEVICES, SUCH AS VCSELS, WITH AN OXIDE CONFINEMENT LAYER

    公开(公告)号:US20220376476A1

    公开(公告)日:2022-11-24

    申请号:US17303050

    申请日:2021-05-19

    Abstract: Methods for forming an at least partially oxidized confinement layer of a semiconductor device and corresponding semiconductor devices are provided. The method comprises forming two or more layers of a semiconductor device on a substrate. The layers include an exposed layer and a to-be-oxidized layer. The to-be-oxidized layer is disposed between the substrate and the exposed layer. The method further comprises etching, using a masking process, a pattern of holes that extend through the exposed layer at least to a first surface of the to-be-oxidized layer. Each hole of the pattern of holes extends in a direction that is transverse to a level plane that is parallel to the first surface of the to-be-oxidized layer. The method further comprises oxidizing the to-be-oxidized layer through the pattern of holes by exposing the two or more layers of the semiconductor device to an oxidizing gas to form a confinement layer.

    TUNNEL JUNCTION PATTERNING FOR CONTROLLING OPTICAL AND CURRENT CONFINEMENT IN A VERTICAL-CAVITY SURFACE-EMITTING LASER

    公开(公告)号:US20240380184A1

    公开(公告)日:2024-11-14

    申请号:US18144984

    申请日:2023-05-09

    Abstract: Some embodiments of the present invention are directed to a tunnel junction for a vertical-cavity surface-emitting laser (VCSEL) that controls optical and current confinement within the VCSEL. The tunnel junction may define an electrical current injection area and an optical aperture for the VCSEL and may include a heavily p++ doped p-type material and a heavily n++ doped n-type material disposed on the p-type material. At least a portion of the outer edges of the n-type material are etched such that the n-type material has a cross-sectional area that is less than a cross-sectional area of the p-type material. By removing a portion of n-type material near the outer edge of the tunnel junction, a sloped effective refractive index is formed, and an effective area of the tunnel junction is changed, which increases the overlap of the current density and the optical field of the VCSEL.

    VERTICAL-CAVITY SURFACE-EMITTING LASER (VCSEL) WITH CASCADED ACTIVE REGION

    公开(公告)号:US20210184432A1

    公开(公告)日:2021-06-17

    申请号:US17247401

    申请日:2020-12-10

    Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.

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