公开(公告)号：US11217291B2

公开(公告)日：2022-01-04

申请号：US16508772

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C7/08 ,  G11C7/12 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US12094533B2

公开(公告)日：2024-09-17

申请号：US17877613

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0057

Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

公开(公告)号：US20210012825A1

公开(公告)日：2021-01-14

申请号：US16508772

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/408 ,  G11C11/4091

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US20250054543A1

公开(公告)日：2025-02-13

申请号：US18812133

申请日：2024-08-22

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

公开(公告)号：US20220199137A1

公开(公告)日：2022-06-23

申请号：US17563389

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G11C7/12 ,  G11C7/08

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US20160086662A1

公开(公告)日：2016-03-24

申请号：US14954587

申请日：2015-11-30

Applicant: Micron Technology, Inc.

Inventor： Marco Ferrario ,  Christophe Vincent Antoine Laurent ,  Francesco Mastroianni

IPC: G11C13/00

CPC classification number: G11C8/12 ,  G06F12/0802 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/22 ,  G11C8/18 ,  G11C11/21 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/04

Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.

Abstract translation: 存储器件包括具有从行地址缓冲器提供上行地址的相位的操作，将上行地址与下行地址组合以选择行数据缓冲器的数据的相位和输出数据的相位 从行数据缓冲器，其中激活命令开始并且随后的激活命令被忽略，直到经过预设时间。

公开(公告)号：US20240038301A1

公开(公告)日：2024-02-01

申请号：US17877613

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0057

Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

公开(公告)号：US09405475B2

公开(公告)日：2016-08-02

申请号：US14534938

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giulio Albini ,  Emanuele Confalonieri ,  Francesco Mastroianni

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/16 ,  G06F3/06 ,  G11C11/56 ,  G11C13/00

CPC classification number: G06F3/0613 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/1663 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/5678 ,  G11C13/0004

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及多通道存储器件以及选择其一个或多个通道的方法。

公开(公告)号：US20150067254A1

公开(公告)日：2015-03-05

申请号：US14534938

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giuliu Albini ,  Emanuele Confalonieri ,  Francesco Mastroianni

IPC: G06F3/06 ,  G11C11/56

CPC classification number: G06F3/0613 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/1663 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/5678 ,  G11C13/0004

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及多通道存储器件以及选择其一个或多个通道的方法。

公开(公告)号：US20240071483A1

公开(公告)日：2024-02-29

申请号：US17898392

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Francesco Mastroianni ,  Andrea Martinelli ,  Efrem Bolandrina ,  Lucia Di Martino ,  Riccardo Muzzetto ,  Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C11/56 ,  G06F3/06 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G06F3/0679 ,  G06F12/0246

Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.