公开(公告)号：US20250125274A1

公开(公告)日：2025-04-17

申请号：US18988440

申请日：2024-12-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L23/538 ,  G11C5/06 ,  H10B12/00

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

公开(公告)号：US12262532B2

公开(公告)日：2025-03-25

申请号：US18429004

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  H01L25/065 ,  H10B80/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US12254967B2

公开(公告)日：2025-03-18

申请号：US17411801

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Deepti Verma ,  Shruthi Kumara Vadivel

IPC: G16H20/00 ,  G16H10/60 ,  G16H50/20

Abstract: Methods and non-transitory machine-readable media associated with treatment plan identification are described. Treatment plan identification can include receiving first signaling configured to monitor user health data and receiving second signaling configured to monitor user behavior data. Treatment plan identification can include writing data that is based at least in part on a combination of the first signaling and the second signaling and identifying output data representative of a treatment plan for the user based at least in part on input data representative of the written data and additional user data. Output data representative of the treatment plan can be transmitted to a computing device accessible by the user, a computing device accessible by a provider, or both.

公开(公告)号：US12242346B2

公开(公告)日：2025-03-04

申请号：US17937924

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Fatma Arzum Simsek-Ege

IPC: G06F11/10 ,  G11C29/00

Abstract: Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.

公开(公告)号：US12114500B2

公开(公告)日：2024-10-08

申请号：US17946837

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B99/00

CPC classification number: H10B43/27 ,  H01L21/31111 ,  H01L21/32134 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B99/00

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

公开(公告)号：US12113015B2

公开(公告)日：2024-10-08

申请号：US17396341

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L23/525 ,  G11C29/00 ,  H10B12/00 ,  G11C11/4096

CPC classification number: H01L23/5256 ,  H10B12/50 ,  G11C11/4096

Abstract: Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.

公开(公告)号：US20240290374A1

公开(公告)日：2024-08-29

申请号：US18409714

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Beau D. Barry

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097

Abstract: A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240274562A1

公开(公告)日：2024-08-15

申请号：US18630883

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Beau D. Barry

IPC: H01L23/00 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  G11C11/4085 ,  G11C11/4091 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20240274184A1

公开(公告)日：2024-08-15

申请号：US18632024

申请日：2024-04-10

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  G11C11/22 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US11984150B2

公开(公告)日：2024-05-14

申请号：US17821646

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/40 ,  G11C11/22 ,  G11C11/408 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4085 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/4087 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.