公开(公告)号：US20210313339A1

公开(公告)日：2021-10-07

申请号：US17347412

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Qian Tao ,  Matthew N. Rocklein ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L49/02 ,  H01L45/00

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

公开(公告)号：US20210151676A1

公开(公告)日：2021-05-20

申请号：US17162071

申请日：2021-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsz W. Chan ,  D. V. Nirmal Ramaswamy ,  Qian Tao ,  Yongjun J. Hu ,  Everett A. McTeer

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

公开(公告)号：US10541252B2

公开(公告)日：2020-01-21

申请号：US16410973

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/792

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190386015A1

公开(公告)日：2019-12-19

申请号：US16550983

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Qian Tao ,  Matthew N. Rocklein ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L45/00 ,  H01L49/02

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

公开(公告)号：US10193064B2

公开(公告)日：2019-01-29

申请号：US15642673

申请日：2017-07-06

Applicant: Micron Technology, Inc.

Inventor： Tsz W. Chan ,  D. V. Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

公开(公告)号：US11289487B2

公开(公告)日：2022-03-29

申请号：US15903964

申请日：2018-02-23

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  Paul A. Paduano ,  Sanket S. Kelkar ,  Christopher W. Petz ,  Zhe Song ,  Vassil Antonov ,  Qian Tao

IPC: H01L27/108 ,  H01L21/285 ,  H01L49/02

Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

公开(公告)号：US10923658B2

公开(公告)日：2021-02-16

申请号：US16440718

申请日：2019-06-13

Applicant: Micron Technology, Inc.

Inventor： Shuichiro Yasuda ,  Noel Rocklein ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Qian Tao

IPC: H01L45/00

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

公开(公告)号：US20190296235A1

公开(公告)日：2019-09-26

申请号：US16440718

申请日：2019-06-13

Applicant: Micron Technology, Inc.

Inventor： Shuichiro Yasuda ,  Noel Rocklein ,  Scott E. Sills ,  Durai Vishal Nirmal Ramaswamy ,  Qian Tao

IPC: H01L45/00

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

公开(公告)号：US10388871B2

公开(公告)日：2019-08-20

申请号：US15334186

申请日：2016-10-25

Applicant: Micron Technology, Inc.

Inventor： Shuichiro Yasuda ,  Noel Rocklein ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Qian Tao

IPC: H01L45/00

Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

公开(公告)号：US20190189626A1

公开(公告)日：2019-06-20

申请号：US16284475

申请日：2019-02-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/11502 ,  H01G4/008 ,  H01G4/40 ,  H01G4/33 ,  H01G4/08 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.