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    Non-volatile memory
    1.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号：US08937347B2

    公开(公告)日：2015-01-20

    申请号：US14266079

    申请日：2014-04-30

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

    IPC: H01L21/4763 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

    Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

    Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

    NON-VOLATILE MEMORY
    2.
    发明申请
    NON-VOLATILE MEMORY 有权
    非易失性存储器

    公开(公告)号：US20140231900A1

    公开(公告)日：2014-08-21

    申请号：US14266079

    申请日：2014-04-30

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

    IPC: H01L29/792

    CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

    Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

    Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160133718A1

    公开(公告)日：2016-05-12

    申请号：US14539768

    申请日：2014-11-12

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

    Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

    Abstract translation: 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。

    Non-volatile memory and manufacturing method thereof
    6.
    发明授权
    Non-volatile memory and manufacturing method thereof 有权
    非易失性存储器及其制造方法

    公开(公告)号：US08748963B1

    公开(公告)日：2014-06-10

    申请号：US13707426

    申请日：2012-12-06

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

    IPC: H01L21/4763

    CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

    Abstract translation: 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190067246A1

    公开(公告)日：2019-02-28

    申请号：US15683850

    申请日：2017-08-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Guan-Wei Wu ,  Chu-Yung Liu ,  Yao-Wen Chang ,  I-Chen Yang

    IPC: H01L25/065 ,  H01L21/02 ,  H01L21/768

    Abstract: A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.

    Operation method of multi-level memory
    9.
    发明授权
    Operation method of multi-level memory 有权
    多层内存的操作方法

    公开(公告)号：US09208892B2

    公开(公告)日：2015-12-08

    申请号：US13943691

    申请日：2013-07-16

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

    Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

    Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。

    Memory device and operation method thereof
    10.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US11798639B2

    公开(公告)日：2023-10-24

    申请号：US17531825

    申请日：2021-11-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  Chun-Liang Lu ,  I-Chen Yang

    IPC: G11C7/00 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483

    Abstract: A memory device and an operation method thereof are disclosed. The memory device includes a P-well region, a common source line, a ground selection line, at least one dummy ground selection line, a plurality of word lines, at least one dummy string selection line, a string selection line, at least one bit line and at least one memory string. The gates of a plurality of memory cells of the memory string are connected to the word lines. The operation method includes the following steps. Performing a read operation and applying a read voltage on the selected word line. Applying a pass voltage on other unselected word lines and the ground selection lines, etc. Before ending of the read operation, firstly decreasing voltages of the string selection line and the dummy string selection line in advance, then increasing voltage of the bit line.

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