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    TEMPERATURE-CONTROLLED DEPTH OF RELEASE LAYER
    1.
    发明申请
    TEMPERATURE-CONTROLLED DEPTH OF RELEASE LAYER 审中-公开
    释放层的温度控制深度

    公开(公告)号：US20130269860A1

    公开(公告)日：2013-10-17

    申请号：US13448939

    申请日：2012-04-17

    申请人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Maha M. Khayyat ,  Norma E. Sosa Cortes ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： B32B38/00 ,  B05D3/02

    CPC分类号： B32B38/10 ,  B32B2457/14 ,  H01L21/02002 ,  H01L21/304 ,  H01L21/6836 ,  H01L31/1892 ,  Y02E10/50

    摘要： A stressor layer is formed atop a base substrate at a first temperature which induces a first tensile stress in the base substrate that is below a fracture toughness of base substrate. The base substrate and the stressor layer are then brought to a second temperature which is less than the first temperature. The second temperature induces a second tensile stress in the stressor layer which is greater than the first tensile stress and which is sufficient to allow for spalling mode fracture to occur within the base substrate. The base substrate is spalled at the second temperature to form a spalled material layer. Spalling occurs at a fracture depth which is dependent upon the fracture toughness of the base substrate, stress level within the base substrate, and the second tensile stress of the stressor layer induced at the second temperature.

    摘要翻译： 在第一温度下在基底顶部形成应力层，该第一温度在基础基板中引起低于基底基板的断裂韧性的第一拉伸应力。 然后使基底和应力层达到小于第一温度的第二温度。 第二温度在应力层中引起第二拉伸应力，其大于第一拉伸应力，并且其足以允许在基底基底内发生剥落模式断裂。 基底基板在第二温度下剥离以形成剥离的材料层。 剥离发生在取决于基底的断裂韧性，基底衬底内的应力水平以及在第二温度下引起的应力层的第二拉伸应力的断裂深度。

    EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY
    3.
    发明申请
    EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY 有权
    用于改善基板可重复性的边缘排除方法

    公开(公告)号：US20130005116A1

    公开(公告)日：2013-01-03

    申请号：US13172793

    申请日：2011-06-29

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

    IPC分类号： H01L21/301

    CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

    摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

    摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

    Edge-exclusion spalling method for improving substrate reusability
    4.
    发明授权
    Edge-exclusion spalling method for improving substrate reusability 有权
    用于提高底物可重用性的边缘排除剥落方法

    公开(公告)号：US08748296B2

    公开(公告)日：2014-06-10

    申请号：US13172793

    申请日：2011-06-29

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

    IPC分类号： H01L21/00

    CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

    摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

    摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

    Single-junction photovoltaic cell
    6.
    发明授权
    Single-junction photovoltaic cell 有权
    单结光伏电池

    公开(公告)号：US08633097B2

    公开(公告)日：2014-01-21

    申请号：US12713572

    申请日：2010-02-26

    申请人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

    发明人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

    IPC分类号： H01L21/22 ,  H01L21/38 ,  H01L21/385

    CPC分类号： H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    摘要： A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

    摘要翻译： 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

    Single-Junction Photovoltaic Cell
    7.
    发明申请
    Single-Junction Photovoltaic Cell 有权
    单相光伏电池

    公开(公告)号：US20100307591A1

    公开(公告)日：2010-12-09

    申请号：US12713572

    申请日：2010-02-26

    申请人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

    发明人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

    IPC分类号： H01L31/0304 ,  H01L31/18

    CPC分类号： H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    摘要： A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

    摘要翻译： 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

    High-quality SGOI by annealing near the alloy melting point
    8.
    发明授权
    High-quality SGOI by annealing near the alloy melting point 失效
    高品质SGOI通过在合金熔点附近退火

    公开(公告)号：US07679141B2

    公开(公告)日：2010-03-16

    申请号：US12027561

    申请日：2008-02-07

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

    IPC分类号： H01L31/392

    CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

    摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

    摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

    Use of thin SOI to inhibit relaxation of SiGe layers
    9.
    发明授权
    Use of thin SOI to inhibit relaxation of SiGe layers 有权
    使用薄SOI抑制SiGe层的弛豫

    公开(公告)号：US06989058B2

    公开(公告)日：2006-01-24

    申请号：US10654232

    申请日：2003-09-03

    申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

    IPC分类号： C30B25/02

    CPC分类号： H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

    摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

    摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。