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122 条记录 (耗时 0.031 秒)

    Semiconductor device and method for fabricating the same
    3.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06580125B2

    公开(公告)日：2003-06-17

    申请号：US10204097

    申请日：2002-08-15

    申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

    发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

    IPC分类号： H01L2976

    CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

    摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

    摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。

    Field effect transistor and method of manufacturing the same
    6.
    发明授权
    Field effect transistor and method of manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US06504176B2

    公开(公告)日：2003-01-07

    申请号：US09824922

    申请日：2001-04-03

    申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

    发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

    IPC分类号： H01L310317

    CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

    摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.

    摘要翻译： 提供具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底，形成在n型衬底上的n型半导体层，形成在n型半导体层上的p型半导体层，嵌入在n型衬底中的p型区域， 埋入n型半导体层和p型半导体层的n型区域，在其表面侧配置在p型半导体层中的n型源极区域，设置在p型半导体层上的绝缘层 p型半导体层，设置在绝缘层上的栅电极，源电极和漏电极。 n型半导体层，p型半导体层和p型区域分别由具有至少2eV的带隙的宽间隙半导体制成。

    Equipment for communication system
    7.
    发明授权
    Equipment for communication system 有权
    通讯系统设备

    公开(公告)号：US06654604B2

    公开(公告)日：2003-11-25

    申请号：US09989270

    申请日：2001-11-20

    申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

    发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

    IPC分类号： H04Q720

    CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

    摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

    摘要翻译： 用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。 第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。 第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。 由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

    Semiconductor device having an active region of alternating layers
    8.
    发明授权
    Semiconductor device having an active region of alternating layers 有权
    具有交替层的有源区的半导体器件

    公开(公告)号：US06989553B2

    公开(公告)日：2006-01-24

    申请号：US10625256

    申请日：2003-07-23

    申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    IPC分类号： H01L31/0312

    CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

    摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

    摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

    MISFET
    9.
    发明授权
    MISFET 有权

    公开(公告)号：US06864507B2

    公开(公告)日：2005-03-08

    申请号：US10459807

    申请日：2003-06-12

    申请人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

    发明人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

    IPC分类号： H01L21/04 ,  H01L29/10 ,  H01L29/24 ,  H01L29/36 ,  H01L29/772 ,  H01L29/78 ,  H01L31/0312

    CPC分类号： H01L29/7813 ,  H01L21/0455 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

    摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

    摘要翻译： P型有源区12; n型源极/漏极区域13a和13b; 由热氧化膜制成的栅极绝缘膜14; 栅电极15; 源极/漏电极16a和16b设置在p型SiC衬底11上。在有源区12中，足够薄以产生量子效应的p型重掺杂层12a和厚的未掺杂层12b交替 堆叠 当载流子流动时，杂质离子在有源区中的散射减小，并且沟道迁移率增加。 在OFF状态下，耗尽层在整个有源区扩展，并且击穿电压增加。 由于栅极绝缘膜中俘获的电荷减少或栅极绝缘膜与有源区之间的界面附近的结果，沟道迁移率进一步增加。

    Semiconductor device having an active region of alternating layers
    10.
    发明授权
    Semiconductor device having an active region of alternating layers 有权
    具有交替层的有源区的半导体器件

    公开(公告)号：US06690035B1

    公开(公告)日：2004-02-10

    申请号：US09980598

    申请日：2001-11-01

    申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    IPC分类号： H01L310312

    CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

    摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

    摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。