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    Semiconductor element, semiconductor device, and power converter
    1.
    发明授权
    Semiconductor element, semiconductor device, and power converter 有权
    半导体元件，半导体器件和功率转换器

    公开(公告)号：US08410489B2

    公开(公告)日：2013-04-02

    申请号：US13266271

    申请日：2010-04-28

    申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

    发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

    IPC分类号： H01L29/24

    CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

    摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

    摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的碳化硅半导体衬底10，半导体层20 第一导电类型的体区30，第一导电类型的源极区40，与体区接触的外延沟道层50，源电极45，栅极绝缘膜60， 栅电极65和漏电极70.如果施加到MISFET的栅电极的电压小于阈值电压，则半导体元件100用作二极管，其中电流从源电极45流到漏电极70通过 外延沟道层50.该二极管的导通电压的绝对值小于体二的导通电压的绝对值 由所述体区和所述第一碳化硅半导体层形成。

    Semiconductor device with silicon carbide epitaxial layer including dopant profiles for reducing current overconcentration
    2.
    发明授权
    Semiconductor device with silicon carbide epitaxial layer including dopant profiles for reducing current overconcentration 有权
    具有碳化硅外延层的半导体器件包括用于减少电流超过浓度的掺杂剂轮廓

    公开(公告)号：US07982224B2

    公开(公告)日：2011-07-19

    申请号：US12518483

    申请日：2008-10-10

    申请人： Chiaki Kudou ,  Osamu Kusumoto ,  Koichi Hashimoto

    发明人： Chiaki Kudou ,  Osamu Kusumoto ,  Koichi Hashimoto

    IPC分类号： H01L29/15

    CPC分类号： H01L29/0847 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828

    摘要： A semiconductor device includes: a semiconductor substrate of silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type, which has been grown on the principal surface of the substrate; well regions of a second conductivity type, which form parts of the silicon carbide epitaxial layer; and source regions of the first conductivity type, which form respective parts of the well regions. A channel epitaxial layer of silicon carbide is grown over the well regions and source regions of the silicon carbide epitaxial layer. A portion of the channel epitaxial layer located over the well regions functions as a channel region. A dopant of the first conductivity type is implanted into the other portions and of the channel epitaxial layer except the channel region.

    摘要翻译： 半导体器件包括：第一导电类型的碳化硅半导体衬底; 已经在基板的主表面上生长的第一导电类型的碳化硅外延层; 第二导电类型的阱区，其形成碳化硅外延层的一部分; 和第一导电类型的源区，其形成阱区的各个部分。 在碳化硅外延层的阱区和源极区上生长碳化硅的沟道外延层。 位于阱区之上的沟道外延层的一部分用作沟道区。 第一导电类型的掺杂剂注入到沟道区以外的其它部分和沟道外延层中。

    Semiconductor device and production method therefor
    3.
    发明授权
    Semiconductor device and production method therefor 有权
    半导体装置及其制造方法

    公开(公告)号：US07816688B2

    公开(公告)日：2010-10-19

    申请号：US10494616

    申请日：2002-11-27

    申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

    发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

    IPC分类号： H01L29/51

    CPC分类号： H01L21/28185 ,  H01L21/049 ,  H01L21/28202 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7838

    摘要： An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.

    摘要翻译： SIC基板1的上部在氧气气氛中在800〜1400℃的温度下氧化，在1.4×102Pa以下，由此形成作为热氧化膜的第一绝缘膜2 nm以下的厚度。 然后，进行退火，然后通过CVD在其上形成厚度为约5nm的氮化物膜的第一盖层3。 作为厚度约130nm的氧化物膜的第二绝缘膜4通过CVD沉积在其上。 在其上形成厚度为约10nm的氮化膜的第二盖层5。 以这种方式，形成通过第二盖层5由第一绝缘膜2制成的栅极绝缘膜6，从而获得低损耗高可靠性的半导体器件。

    SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20100055858A1

    公开(公告)日：2010-03-04

    申请号：US12516858

    申请日：2008-07-18

    申请人： Masashi Hayashi ,  Kazuya Utusnomiya ,  Osamu Kusumoto

    发明人： Masashi Hayashi ,  Kazuya Utusnomiya ,  Osamu Kusumoto

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7828 ,  H01L21/0485 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

    摘要： A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.

    摘要翻译： 根据本发明的半导体器件包括具有碳化硅半导体层的碳化硅半导体衬底; 设置在碳化硅半导体层中并包含p型杂质的p型杂质区; 电连接到p型杂质区的p型欧姆电极; 设置在与所述p型杂质区相邻的所述碳化硅半导体层中的n型杂质区，并且包含n型杂质; 和与n型杂质区电连接的n型欧姆电极。 p型欧姆电极含有镍，铝，硅和碳的合金，n型欧姆电极含有钛，硅和碳的合金。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06995397B2

    公开(公告)日：2006-02-07

    申请号：US10466353

    申请日：2002-09-17

    申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

    发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

    IPC分类号： H01L31/072

    CPC分类号： H01L29/66068 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838

    摘要： A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

    摘要翻译： 具有堆积通道SiC-MISFET结构的半导体器件包括形成在SiC衬底上的p型SiC层10，n型沟道层20，栅极绝缘膜11，栅电极12和n型源， 漏极层13a和13b。 沟道层20包括未掺杂层22和形成在未掺杂层22的下端附近的δ掺杂层21.由于沟道层20在其较深部分包括高浓度δ掺杂层21， 沟道层的表面区域的电场减弱，从而允许电流驱动力增加。

    Probe for scanning tunneling microscope and manufacturing method thereof
    9.
    发明授权
    Probe for scanning tunneling microscope and manufacturing method thereof 失效
    扫描隧道显微镜探针及其制造方法

    公开(公告)号：US5357109A

    公开(公告)日：1994-10-18

    申请号：US65899

    申请日：1993-05-25

    申请人： Osamu Kusumoto

    发明人： Osamu Kusumoto

    IPC分类号： C01G9/02 ,  G01B7/34 ,  G01B21/00 ,  G01N27/00 ,  G01N37/00 ,  G01Q30/10 ,  G01Q60/16 ,  G01Q70/08 ,  H01J9/14 ,  H01J37/26 ,  H01J37/28

    CPC分类号： G01Q60/16 ,  B82Y15/00 ,  B82Y35/00 ,  G01Q70/12 ,  Y10S977/878 ,  Y10S977/879

    摘要： A probe for a scanning tunneling microscope and manufacturing method therefor in which tetrapod-shaped whiskers of zinc oxide are placed on a conductive material which is adhered on a tip part of a fine wire of platinized iridium in a manner that three legs of the tetrapod contact the conductive material; the conductive material is heated for melting only the conductive material; and cooling the melted conductive material for being hardened, thereby the stem part of the whisker is inserted into the conductive material.

    摘要翻译： 用于扫描隧道显微镜的探针及其制造方法，其中将氧化锌的四足形晶须放置在导电材料上，该导电材料以四极接触的三条腿的方式粘附在镀铂铱细线的末端部分 导电材料; 导电材料被加热仅熔化导电材料; 并将熔融的导电材料冷却以进行硬化，从而将晶须的茎部插入到导电材料中。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20100295060A1

    公开(公告)日：2010-11-25

    申请号：US12518483

    申请日：2008-10-10

    申请人： Chiaki Kudou ,  Osamu Kusumoto ,  Koichi Hashimoto

    发明人： Chiaki Kudou ,  Osamu Kusumoto ,  Koichi Hashimoto

    IPC分类号： H01L29/808 ,  H01L21/337

    CPC分类号： H01L29/0847 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828

    摘要： A semiconductor device 100 includes: a semiconductor substrate 10 of silicon carbide of a first conductivity type; a silicon carbide epitaxial layer 20 of the first conductivity type, which has been grown on the principal surface 10a of the substrate 10; well regions 22 of a second conductivity type, which form parts of the silicon carbide epitaxial layer 20; and source regions 24 of the first conductivity type, which form respective parts of the well regions 22. A channel epitaxial layer 30 of silicon carbide has been grown over the well regions 22 and source regions 24 of the silicon carbide epitaxial layer 20. A portion of the channel epitaxial layer 30 that is located over the well regions 22 functions as a channel region 40. And a dopant of the first conductivity type has been implanted into the other portions 33 and 35 of the channel epitaxial layer 30 except the channel region 40.

    摘要翻译： 半导体器件100包括：第一导电类型的碳化硅的半导体衬底10; 已经在衬底10的主表面10a上生长的第一导电类型的碳化硅外延层20; 第二导电类型的阱区22，其形成碳化硅外延层20的一部分; 以及形成阱区22的相应部分的第一导电类型的源极区24.已经在碳化硅外延层20的阱区22和源极区24上生长了碳化硅的沟道外延层30.一部分 位于阱区22上方的沟道外延层30用作沟道区40.第一导电类型的掺杂剂已经被注入到沟道外延层30的除了沟道区40之外的其它部分33和35中 。