公开(公告)号：US06995396B2

公开(公告)日：2006-02-07

申请号：US10279119

申请日：2002-10-24

申请人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

IPC分类号： H01L31/0312 ,  H01L29/80 ,  H01L31/112 ,  H01L29/76 ,  H01L27/095

CPC分类号： H01L29/365 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/0445 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat δ-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

公开(公告)号：US06900483B2

公开(公告)日：2005-05-31

申请号：US10162503

申请日：2002-06-04

申请人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

发明人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

IPC分类号： H01L21/329 ,  H01L29/24 ,  H01L29/872 ,  H01L29/80

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

摘要翻译： 肖特基二极管包括由4H-SiC制成的半导体衬底，外延生长的4H-SiC层，离子注入层，肖特基电极，欧姆电极和由热氧化膜制成的绝缘层。 肖特基电极和绝缘层彼此不接触，其间设置有间隙，由此不发生改变的层。 因此，可以抑制泄漏电流的发生。

公开(公告)号：US06600203B2

公开(公告)日：2003-07-29

申请号：US10127126

申请日：2002-04-22

申请人： Kunimasa Takahashi ,  Toshiya Yokogawa ,  Makoto Kitabatake ,  Masao Uchida ,  Osamu Kusumoto ,  Kenya Yamashita

发明人： Kunimasa Takahashi ,  Toshiya Yokogawa ,  Makoto Kitabatake ,  Masao Uchida ,  Osamu Kusumoto ,  Kenya Yamashita

IPC分类号： H01L3100

CPC分类号： H01L29/7813 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L29/0878 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/812 ,  H01L29/872

摘要： A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.

摘要翻译： 根据CVD方法，在SiC衬底上形成抑制层，该方法交替重复外延生长未引入杂质的SiC层的未掺杂层的步骤，以及外延生长杂质掺杂层的步骤 其中氮脉冲地引入其中的SiC层。 抑制层中氮的浓度曲线锐利，防止了微管的延伸。 可以通过在抑制层上沉积形成有源区的SiC层来形成适当地使用SiC的高击穿电压和高温可操作性的半导体器件。

公开(公告)号：US06580125B2

公开(公告)日：2003-06-17

申请号：US10204097

申请日：2002-08-15

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L2976

CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。

公开(公告)号：US06940127B2

公开(公告)日：2005-09-06

申请号：US10631086

申请日：2003-07-31

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

IPC分类号： H01L21/82 ,  H01L27/06 ,  H01L29/10 ,  H01L29/15 ,  H01L29/24 ,  H01L29/36 ,  H01L29/772 ,  H01L29/812 ,  H01L29/872 ,  H03D7/12 ,  H03F3/60 ,  H01L29/76

CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of δ-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of δ-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the δ-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

摘要翻译： 用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。 第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。 第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。 由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

公开(公告)号：US06504176B2

公开(公告)日：2003-01-07

申请号：US09824922

申请日：2001-04-03

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

IPC分类号： H01L310317

CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.

摘要翻译： 提供具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底，形成在n型衬底上的n型半导体层，形成在n型半导体层上的p型半导体层，嵌入在n型衬底中的p型区域， 埋入n型半导体层和p型半导体层的n型区域，在其表面侧配置在p型半导体层中的n型源极区域，设置在p型半导体层上的绝缘层 p型半导体层，设置在绝缘层上的栅电极，源电极和漏电极。 n型半导体层，p型半导体层和p型区域分别由具有至少2eV的带隙的宽间隙半导体制成。

公开(公告)号：US07816688B2

公开(公告)日：2010-10-19

申请号：US10494616

申请日：2002-11-27

申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

IPC分类号： H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/049 ,  H01L21/28202 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7838

摘要： An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.

摘要翻译： SIC基板1的上部在氧气气氛中在800〜1400℃的温度下氧化，在1.4×102Pa以下，由此形成作为热氧化膜的第一绝缘膜2 nm以下的厚度。 然后，进行退火，然后通过CVD在其上形成厚度为约5nm的氮化物膜的第一盖层3。 作为厚度约130nm的氧化物膜的第二绝缘膜4通过CVD沉积在其上。 在其上形成厚度为约10nm的氮化膜的第二盖层5。 以这种方式，形成通过第二盖层5由第一绝缘膜2制成的栅极绝缘膜6，从而获得低损耗高可靠性的半导体器件。

公开(公告)号：US07786565B2

公开(公告)日：2010-08-31

申请号：US10536828

申请日：2004-09-06

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L23/492

CPC分类号： H01L23/3735 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

摘要翻译： 半导体装置包括半导体芯片61，其包括使用宽带隙半导体的功率半导体器件，基底材料62和63，第一和第二中间构件65和68a，导热构件66，辐射翅片67和封装材料 用于封装半导体芯片61，第一和第二中间构件65和68a以及导热构件66.基材62和63的顶端分别作为外部连接端子62a和63a工作。 第二中间构件68a由比第一中间构件65低导热性的材料制成，并且与第一中间构件相比，第二中间构件68a的与半导体芯片61的接触面积更大。

公开(公告)号：US06995397B2

公开(公告)日：2006-02-07

申请号：US10466353

申请日：2002-09-17

申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

IPC分类号： H01L31/072

CPC分类号： H01L29/66068 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838

摘要： A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

摘要翻译： 具有堆积通道SiC-MISFET结构的半导体器件包括形成在SiC衬底上的p型SiC层10，n型沟道层20，栅极绝缘膜11，栅电极12和n型源， 漏极层13a和13b。 沟道层20包括未掺杂层22和形成在未掺杂层22的下端附近的δ掺杂层21.由于沟道层20在其较深部分包括高浓度δ掺杂层21， 沟道层的表面区域的电场减弱，从而允许电流驱动力增加。

公开(公告)号：US07846828B2

公开(公告)日：2010-12-07

申请号：US12338395

申请日：2008-12-18

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。