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1.发明授权Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins 失效用于半导体器件的壳体，半导体器件引脚和用于制造引脚的方法公开(公告)号：US07060534B2
公开(公告)日：2006-06-13
申请号：US10757549
申请日：2004-01-15
IPC分类号： H01L21/44
CPC分类号： H01L23/49582 , H01L2924/0002 , H05K3/3426 , H05K2201/10689 , H05K2201/10909 , Y02P70/613 , H01L2924/00
摘要： A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.
摘要翻译： 一种用于半导体器件的壳体，半导体器件引脚和用于制造引脚的方法，其中至少一个引脚通过一个或多个冲压从基体（特别是引线框架）冲压出来 工艺步骤，其中在所述销的最后冲压之后，销被单独的金属层涂覆。
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公开(公告)号：US07277338B2
公开(公告)日：2007-10-02
申请号：US10487255
申请日：2002-08-21
IPC分类号： G11C7/00
CPC分类号： G11C29/50012 , G11C7/1051 , G11C7/1087 , G11C11/401 , G11C29/50
摘要： A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.
摘要翻译： 一种用于半导体存储器件的测试方法，具有用于数据选通信号的双向数据选通端子，并且在测试装置处具有用于数据信号的至少一个数据端，其至少可以产生数据选通和数据信号，并且还传输和 评估数据信号。 存储器件连接到产生数据选通和数据信号的测试装置，并传送和评估数据信号。 在使用数据选通和数据信号的测试过程中，数据从第一半导体存储器件传送到相同类型的第二半导体存储器件，并且在通过测试装置从第二半导体存储器件读出之后被评估 。
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3.发明授权Integrated semiconductor memory and method for operating a semiconductor memory 失效用于操作半导体存储器的集成半导体存储器和方法公开(公告)号：US07443713B2
公开(公告)日：2008-10-28
申请号：US11331365
申请日：2006-01-13
IPC分类号： G11C11/02
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.
摘要翻译： 集成半导体存储器件包括至少一个存储器单元，至少一个读出放大器和连接到每个读出放大器的一对位线，其中每个存储器单元包括选择晶体管和存储电容器。 每个存储单元的存储电容器包括第一电容器电极和第二电容器电极，并且每个存储单元的选择晶体管包括通过第一接触连接连接到一对位的一个位线的第一源极/漏极区域 与存储单元相对应的线，以及与存储单元的存储电容器的第一电容电极导电连接的第二源/漏区。 每个存储单元的存储电容器的第二电容器电极连接到与存储单元相对应的一对位线的另一位线。
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4.发明授权Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory 失效集成半导体存储器和用于电应力集成半导体存储器的方法公开(公告)号：US07482644B2
公开(公告)日：2009-01-27
申请号：US11061087
申请日：2005-02-18
IPC分类号： H01L29/73
CPC分类号： G11C29/025 , G11C29/02 , H01L27/105 , H01L27/10891
摘要： Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.
摘要翻译： 半导体存储器（1）具有分段字线（5a，5b），它们在每种情况下具有由导电金属制成的主字线（10a，10b）和耦合到主字的多个互连部分（15a，15b） 线路（10a，10b），其通过至少一个接触孔填充物（11）在每种情况下耦合到相应的主字线（10a，10b）。 如果接触孔填充物（11）中的一个有缺陷或高电阻，则会发生半导体存储器的功能错误。 两个相应字线（5a，5b）的互连部分（15a，15b）可以借助于开关单元（20）成对地短路，由此通过接触孔填充物流动的静电流（I） 11）可以用于电接触接触孔填充物（11）。 因此，分段字线的接触孔填充的电应力成为可能。
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公开(公告)号：US07116737B2
公开(公告)日：2006-10-03
申请号：US10253793
申请日：2002-09-24
IPC分类号： H04L7/00
CPC分类号： G04F1/005 , G11C27/024 , H03K5/08 , H03K5/13 , H03K2005/00247
摘要： The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.
摘要翻译： 本发明提供了一种信号通知预定时间值已经过去的装置，具有用于在时钟信号的时间分布中获取和存储时钟信号的振幅值的装置。 提供一种装置，用于连续地将获取和存储的时钟信号的振幅值与时钟信号的瞬时振幅值进行比较，并且用于输出具有第一逻辑状态的比较信号，如果时钟信号的瞬时振幅值小于 存储的振幅值，并且如果时钟信号的瞬时振幅值大于存储的振幅值，则具有第二逻辑状态。 还提供了一种装置，用于对在获取时刻之后发生的比较信号的逻辑状态数进行计数，并且用于发出指示如果计数的逻辑状态数等于预定数量的逻辑状态，则预定时间值已经过去 在时间上对应于预定时间值。
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6.发明授权Integrated semiconductor memory with redundant memory cells replaceable for either true or complementary defective memory cells 有权具有冗余存储器单元的集成半导体存储器，可替换为真或互补缺陷存储器单元公开(公告)号：US07236412B2
公开(公告)日：2007-06-26
申请号：US11053659
申请日：2005-02-09
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C7/1006 , G11C11/401 , G11C29/36 , G11C29/50016 , G11C29/80
摘要： An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.
摘要翻译： 一种集成半导体存储器，包括可以经由第一和第二字线驱动并可由冗余存储器单元代替的存储单元。 在第一存储单元类型中，可以对应于存在于数据输入端的数据存储数据。 在第二存储单元类型的存储单元中，数据可以相对于存在于数据输入端的数据反转存储。 集成半导体存储器包括用于数据反转的电路，其中数据被写入冗余存储单元，相对于存在于数据输入端的数据而被反转，如果有缺陷的存储单元和替换它的冗余存储单元位于不同的 位线的字线条扭曲，并且如果不良存储器单元和替换它的冗余存储器单元与不同的存储器单元类型相关联。
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7.发明授权Integrated dynamic memory having a control circuit for controlling a refresh mode for memory cells 失效具有用于控制存储器单元的刷新模式的控制电路的集成动态存储器公开(公告)号：US06940775B2
公开(公告)日：2005-09-06
申请号：US10823608
申请日：2004-04-14
IPC分类号： G11C8/02 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.
摘要翻译： 集成动态存储器包括被组合以形成单独的可独立寻址单元的存储单元，以及用于控制存储器单元的刷新模式的控制电路。 存储单元可以刷新其存储单元格内容。 控制电路被设计成使得一个或多个单元的存储单元可以在更新周期中并行进行刷新模式。 控制电路基于温度参考值设置要在刷新周期中并行刷新的多个存储单元单元。 可以增加存储器芯片的最大可能工作温度，而不需要对存储器访问的额外限制。
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