公开(公告)号：US10074919B1

公开(公告)日：2018-09-11

申请号：US15625149

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Zhen Zhou ,  Daqiao Du ,  Anne M. Sepic ,  Kai Xiao

IPC: H01R12/00 ,  H01R12/71 ,  H01R12/75 ,  H01R43/20 ,  H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00

CPC classification number: H01R12/714 ,  H01R12/75 ,  H01R43/205 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09545 ,  H05K2201/10265 ,  H05K2201/10909 ,  H05K2203/06 ,  H05K2203/162

Abstract: Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.

公开(公告)号：US09999123B2

公开(公告)日：2018-06-12

申请号：US15075064

申请日：2016-03-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Arata Kishi ,  Tadashi Maeda ,  Tadahiko Sakai

IPC: H05K1/02 ,  H05K1/11 ,  B23K1/00 ,  B23K35/26 ,  B23K35/36 ,  B23K35/362 ,  H05K1/14 ,  H05K1/09 ,  H05K1/00 ,  H05K7/00 ,  H01R12/71

CPC classification number: H05K1/0274 ,  B23K1/0016 ,  B23K35/26 ,  B23K35/264 ,  B23K35/3613 ,  B23K35/362 ,  H01R12/714 ,  H05K1/09 ,  H05K1/092 ,  H05K1/097 ,  H05K1/11 ,  H05K1/111 ,  H05K1/14 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0108 ,  H05K2201/0133 ,  H05K2201/0218 ,  H05K2201/0326 ,  H05K2201/10136 ,  H05K2201/10909 ,  H05K2201/10916 ,  H05K2201/2036 ,  Y02P70/613

Abstract: A connection structure of circuit members includes a first circuit member, a second circuit member, and a joint portion. The first circuit member has a first main surface on which a light-transparent electrode is provided. The second circuit member has a second main surface on which a metal electrode is provided. The joint portion is interposed between the first main surface and the second main surface. The joint portion includes a resin portion and a solder portion. The solder portion electrically connects the light-transparent electrode and the metal electrode. The light-transparent electrode contains an oxide that includes indium and tin, and the solder portion contains bismuth and indium.

公开(公告)号：US09788438B2

公开(公告)日：2017-10-10

申请号：US14368210

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Seol Hee Lim ,  Yun Kyoung Jo ,  Ae Rim Kim ,  Sai Ran Eom ,  Chang Hwa Park

IPC: H01R9/00 ,  H05K3/30 ,  H05K1/11 ,  H05K3/24 ,  C25D3/12 ,  C25D3/16 ,  C25D3/48 ,  C25D3/50 ,  C25D3/56 ,  C25D3/62 ,  C25D5/12 ,  H05K1/09 ,  H05K1/18 ,  H05K3/18 ,  C23C18/16

CPC classification number: H05K3/301 ,  C23C18/1653 ,  C25D3/12 ,  C25D3/16 ,  C25D3/48 ,  C25D3/50 ,  C25D3/562 ,  C25D3/567 ,  C25D3/62 ,  C25D5/12 ,  H05K1/092 ,  H05K1/117 ,  H05K1/18 ,  H05K3/185 ,  H05K3/244 ,  H05K2201/10159 ,  H05K2201/10909 ,  H05K2203/049 ,  H05K2203/1572 ,  Y10T29/49128

Abstract: The printed circuit board for the memory card includes an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.

公开(公告)号：US09633976B1

公开(公告)日：2017-04-25

申请号：US14090993

申请日：2013-11-26

Applicant: University of Notre Dame du Lac

Inventor： Gary H. Bernstein ,  Patrick Fay ,  Wolfgang Porod ,  Qing Liu

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L24/67 ,  H01L23/60 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/66 ,  H01L24/72 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/81141 ,  H01L2224/81224 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/181 ,  H05K1/182 ,  H05K3/326 ,  H05K3/328 ,  H05K2201/0314 ,  H05K2201/10454 ,  H05K2201/10909 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.

公开(公告)号：US09392702B2

公开(公告)日：2016-07-12

申请号：US14792713

申请日：2015-07-07

Applicant: FUJITSU COMPONENT LIMITED

Inventor： Takeshi Okuyama ,  Toshihiro Kusagaya ,  Tohru Yamakami

IPC: B23K1/00 ,  B23K3/06 ,  H05K3/34 ,  H01R4/02 ,  H01R12/57 ,  H01R12/72 ,  H01R13/6587 ,  H05K1/02

CPC classification number: H05K3/3426 ,  H01R4/028 ,  H01R12/57 ,  H01R12/724 ,  H01R13/6587 ,  H05K1/025 ,  H05K3/3494 ,  H05K2201/10189 ,  H05K2201/10757 ,  H05K2201/10803 ,  H05K2201/10909 ,  H05K2201/2081 ,  H05K2203/04 ,  Y02P70/613

Abstract: Disclosed is a surface mount device to be mounted on a base member, including plural lead units, each of the plural lead units including, a lead including a body portion and a foot formed at an end of the lead; a solder portion formed at the foot of the lead to protrude toward the direction of the base member to have a summit portion, and a diffusion prevention portion provided on the lead for preventing a diffusion of a solder along the body portion of the lead.

Abstract translation: 公开了一种表面安装装置，其安装在基座构件上，包括多个引线单元，所述多个引线单元中的每一个包括：引线，其包括形成在引线端部的主体部分和脚部; 形成在引脚的脚部处的焊料部分朝向基部构件的方向突出以具有顶部部分，以及设置在引线上的防止扩散部分，用于防止焊料沿引线的主体部分扩散。

公开(公告)号：US20160039052A1

公开(公告)日：2016-02-11

申请号：US14920772

申请日：2015-10-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： AKIO FURUSAWA ,  KIYOHIRO HINE ,  MASATO MORI ,  TAICHI NAKAMURA

IPC: B23K35/26 ,  H05K1/18 ,  C22C13/00

CPC classification number: B23K35/262 ,  B23K35/0222 ,  B23K35/26 ,  B23K35/40 ,  C22C13/00 ,  H05K1/11 ,  H05K1/111 ,  H05K1/18 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0338 ,  H05K2201/10909

Abstract: Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3≦[Ag]≦4.0, Bi satisfying 0≦[Bi]≦1.0, and Cu satisfying 0

Abstract translation: 包含含有含有Ni的Au电极的Au电极的焊接中使用的焊料包括满足0.3＆nlE的Ag; [Ag]和nlE; 4.0，满足0＆nlE的Bi; [Bi]＆nlE; 1.0，满足0 <[Cu] 其中焊料中Ag，Bi，Cu和In的含量（质量％）分别由[Ag]，[Bi]，[Cu]和[In]表示。 当[Cu]在0 <[Cu] <0.5的范围内时，焊料材料包括In的范围为6.0＆nlE; [In]＆nlE; 6.8; In为5.2+（6-（1.55×[Cu 当Cu [Cu]在[Cu]的范围内时，[Cu]和nlE; 1.0，In的范围为5.2＆nlE; [In]＆nlE; 6.8当[Cu] 落在1.0 <[Cu]和nlE的范围内。 余量仅包括不少于87质量％的Sn。

公开(公告)号：US07867404B2

公开(公告)日：2011-01-11

申请号：US11273789

申请日：2005-11-15

Applicant: Joel Allen Deutsch

Inventor： Joel Allen Deutsch

IPC: C23F1/00

CPC classification number: H05K3/3426 ,  H05K3/26 ,  H05K3/3463 ,  H05K2201/10909 ,  Y02P70/613

Abstract: A method for removing an undesirable material from an electronic or electrical component and introducing a desirable material in place of the undesirable material. The method can include the replacement of a leaded material found on the component with a no-lead material to meet governmental directives including those of the European Union.

Abstract translation: 从电子或电气部件移除不需要的材料并引入所需材料代替不需要的材料的方法。 该方法可以包括使用无铅材料替代部件上发现的含铅材料，以符合包括欧盟在内的政府指令。

公开(公告)号：US07786556B2

公开(公告)日：2010-08-31

申请号：US12215168

申请日：2008-06-25

Applicant: Tomoyuki Yoshino

Inventor： Tomoyuki Yoshino

IPC: H01L21/00

CPC classification number: H05K3/3426 ,  H01L23/49582 ,  H01L2924/0002 ,  H05K2201/10689 ,  H05K2201/10795 ,  H05K2201/10909 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device has an element encapsulated in a resin mold. Metal leads protruding from the resin mold are solder plated except at the lead-tip end surfaces, and the exposed lead-tip end surfaces have an area less than half the cross-sectional area of the protruding metal leads. The semiconductor device is manufactured using a lead frame in which the metal leads are connected to a frame by plating bars having a thickness smaller than half the thickness of the metal leads. In another embodiment, the metal leads are connected to the frame by plating bars that extend sideways from the metal leads, and the end tips of the metal leads are entirely covered with plating to improve soldering wettability.

Abstract translation: 半导体器件具有封装在树脂模具中的元件。 从树脂模具突出的金属引线除了铅尖端面以外是焊料镀覆的，露出的引线前端端面的面积小于突出金属引线的横截面面积的一半。 使用引线框架制造半导体器件，其中金属引线通过具有小于金属引线厚度的一半厚度的电镀棒连接到框架。 在另一个实施例中，金属引线通过从金属引线横向延伸的电镀棒连接到框架，并且金属引线的端部末端被电镀覆盖以提高焊接润湿性。

公开(公告)号：US07616016B2

公开(公告)日：2009-11-10

申请号：US12060753

申请日：2008-04-01

Applicant: Benjamin N. Eldridge ,  Igor Y. Khandros ,  A. Nicholas Sporck

Inventor： Benjamin N. Eldridge ,  Igor Y. Khandros ,  A. Nicholas Sporck

IPC: G01R31/02

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract translation: 在探针卡组件中，可以将一系列探针元件排列在硅空间变压器上。 硅空间变压器可以以与半导体器件的间距相当的非常紧密的间距的主要触点阵列制造。 一个优选的主要接触是弹性弹簧接触。 空间变压器中的导电元件以更放松的间距被路由到第二触点。 在一个优选实施例中，第二触点适于直接连接带状电缆，带状电缆又可连接以提供对每个主触点的选择性连接。 硅空间变压器安装在固定装置中，其提供与待测试的晶片或装置的弹性连接。 可以调整该夹具以使主触头与支撑探针卡板的平面平坦化。

公开(公告)号：US20090272577A1

公开(公告)日：2009-11-05

申请号：US12296735

申请日：2007-04-25

Applicant: Kazuhiro Shiomi ,  Masaaki Ishio

Inventor： Kazuhiro Shiomi ,  Masaaki Ishio

IPC: H01R4/02 ,  H01B1/02

CPC classification number: H05K3/222 ,  H01L23/49582 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01R13/03 ,  H05K3/341 ,  H05K2201/10363 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48

Abstract: A clad material for a wiring connection has an electroconductive layer formed from either pure Cu or a Cu alloy having higher electroconductivity than pure Al, a surface layer formed from either pure Al or an Al alloy and layered on one surface of the electroconductive layer, and a solder layer formed by hot-dip solder plating on the other surface of the electroconductive layer. The wiring connection member has a first connection end provided with an electroconductive layer soldered to an electrode of a semiconductor element, and a second connection end provided with an electroconductive layer soldered to, for example, an external wiring device. The wiring connection member is processed from the clad material for a wiring connection. This wiring member prevents molten solder from depositing on a pressing and heating portion of a local heating apparatus while also possessing excellent solderability.

Abstract translation: 用于布线连接的复合材料具有由纯Cu或具有比纯Al更高的导电性的Cu合金形成的导电层，由纯Al或Al合金形成并且层叠在导电层的一个表面上的表面层，以及 在导电层的另一个表面上通过热浸镀锡形成的焊料层。 布线连接构件具有设置有焊接到半导体元件的电极的导电层的第一连接端和设置有例如外部布线装置的导电层的第二连接端。 布线连接部件由用于布线连接的复合材料加工。 该布线构件防止熔融焊料沉积在局部加热装置的加压和加热部分上，同时还具有优异的可焊性。