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公开(公告)号：US07039838B2
公开(公告)日：2006-05-02
申请号：US10206785
申请日：2002-07-26
摘要： The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a–102N) of the circuit unit (101) to be tested being activated by application of at least one test signal (103) to the word line (102a–102N), the at least one word line (102a–102N) being deactivated by removal of the test signal (103) from the word line (102a–102N), the word lines among all the word lines (102a–102N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.
摘要翻译： 本发明提供了一种用于测试待测试的电路单元（101）的方法，其中测试时间减少，待测试的电路单元（101）的至少一个字线（102a〜102n）被激活， 将至少一个测试信号（103）应用于字线（102a至102n），所述至少一个字线（102a〜102N）通过从所述字线去除所述测试信号（103）而被去激活 （102a〜102N），为了确定激活和去激活的影响，已经读出没有经过激活 - 停止周期的所有字线（102a〜102N）中的字线，并且 测试结果输出。
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2.发明授权Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs 有权用于使用用于多个输入和输出的公共节点来测试存储器芯片的方法和装置公开(公告)号：US07877649B2
公开(公告)日：2011-01-25
申请号：US11934644
申请日：2007-11-02
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
摘要翻译： 提供一种用于测试包括存储器的测试装置的集成装置的装置和方法。 存储器的至少两个数据输入耦合到测试设备的数据输出。 作为替代，存储器的至少两个数据输出耦合到测试设备的数据输入。 测试数据从测试设备传输到存储器芯片并写入存储器的存储单元。 从存储器的存储单元读取数据并从存储器传送到测试设备。 将从存储器芯片读取的数据与写入存储器的测试数据进行比较，以识别存储器的故障。
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3.发明授权Memory and method for improving the reliability of a memory having a used memory region and an unused memory region 失效用于提高具有使用的存储器区域和未使用的存储器区域的存储器的可靠性的存储器和方法公开(公告)号：US07512023B2
公开(公告)日：2009-03-31
申请号：US11541442
申请日：2006-09-29
申请人： Manfred Proell , Stephan Schroeder
发明人： Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C29/88 , G11C29/883
摘要： A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.
摘要翻译： 一种用于提高具有使用的存储区域和未使用的存储器区域的存储器的可靠性的方法，其中所使用的存储器区域中的缺陷存储器元件可以由未使用的存储器区域中的功能存储元件代替，具有提供使用的存储器的步骤 具有第一应力序列的区域; 以及为第二应力序列提供未使用的存储区域。
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公开(公告)号：US20080219060A1
公开(公告)日：2008-09-11
申请号：US11962925
申请日：2007-12-21
申请人： Tobias Graf , Manfred Proell , Stephan Schroeder , Stefan Tuebel
发明人： Tobias Graf , Manfred Proell , Stephan Schroeder , Stefan Tuebel
CPC分类号： G11C29/006 , G11C29/12005
摘要： A memory device and method for internal voltage monitoring is disclosed. One embodiment includes at least one error register configured to store a particular error flag during the stress test. This error flag is generated if the supply voltage applied at the memory device during the test method in the memory device or an internally generated voltage of the memory device lies below a predetermined threshold value.
摘要翻译： 公开了用于内部电压监视的存储器件和方法。 一个实施例包括配置成在压力测试期间存储特定错误标志的至少一个错误寄存器。 如果在存储器件中的测试方法期间在存储器件处施加的电源电压或存储器件的内部产生的电压的电源电压低于预定阈值，则产生该错误标志。
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5.发明申请公开(公告)号：US20050057982A1
公开(公告)日：2005-03-17
申请号：US10911230
申请日：2004-08-04
IPC分类号： G11C8/08 , G11C11/406 , G11C11/408 , H03L7/00
CPC分类号： G11C7/04 , G11C8/08 , G11C11/406 , G11C11/4085 , G11C2211/4068
摘要： A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.
摘要翻译： 半导体存储器包括具有存储电容器的存储单元（2）和具有电极的晶体管，该电极可与两个不同的电位（V1，V2）电偏置，以便打开和闭合晶体管。 用于晶体管截止状态的电极电位（V2）是依赖于温度的电位，其值由半导体存储器（1）温度控制，使得第二电位（V2）变得更加不同于 随着温度（T）的第一电位（V1）增加。
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6.发明授权Integrated semiconductor memory and method for operating an integrated semiconductor memory 有权用于操作集成半导体存储器的集成半导体存储器和方法公开(公告)号：US07248536B2
公开(公告)日：2007-07-24
申请号：US11245455
申请日：2005-10-06
IPC分类号： G11C8/00
CPC分类号： G11C29/025 , G11C7/18 , G11C8/08 , G11C11/401 , G11C11/4085 , G11C11/4097 , G11C29/02 , G11C2029/1202
摘要： A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).
摘要翻译： 至少以测试方式，提供半导体存储器和用于依次操作的方法，以不经由用于去激活的第一行（21）去激活分段字线的字线段（12），而是 经由第二行（22）经由字线段（12）被另外激活。 第二行（22）可以可选地被提供用于激活或第三电位（Vgnd）的第二电位（Vpp）偏置。 如果第三电位（Vgnd）用于至少暂时禁用字线段（12），则可以经由将字线段耦合到第二线路（22）的开关元件（17）来驱动字线段， ，而驱动器段（20）的互补开关元件（16）必须用于去激活。 因此，可以确定驱动器段的两个开关元件（16,17）中的哪一个有缺陷，以及由于浮动电位的永久替换字线，半导体存储器是否以没有错误的方式起作用 经测试的字线段（12）。
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公开(公告)号：US20070070758A1
公开(公告)日：2007-03-29
申请号：US11534400
申请日：2006-09-22
申请人： Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
发明人： Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C8/10 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a conductive state for a differently long time and/or differently strongly, depending on the respective operating mode of the semiconductor memory.
摘要翻译： 公开了一种使用至少一个读出放大器和用于将读出放大器切换至至少一条线路的装置来操作半导体存储器和半导体存储器的方法。 这意味着，根据半导体存储器的相应工作模式，在感测放大器切换到线路期间，其处于不同长时间和/或不同程度的导通状态。
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8.发明授权公开(公告)号：US07120074B2
公开(公告)日：2006-10-10
申请号：US10911230
申请日：2004-08-04
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C8/08 , G11C11/406 , G11C11/4085 , G11C2211/4068
摘要： A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.
摘要翻译： 半导体存储器包括具有存储电容器的存储单元（2）和具有电极的晶体管，该电极可与两个不同的电位（V 1，V 2）电偏置，以便打开和闭合晶体管。 用于晶体管截止状态的电极电位（V 2）是依赖于温度的温度的电位，其值由半导体存储器（1）温度控制，使得第二电位（V 2）变得更大 与温度（T）增加时不同于第一电位（V 1）。
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9.发明申请Semiconductor circuit and arrangement and method for monitoring fuses of a semiconductor circuit 审中-公开用于监测半导体电路的熔丝的半导体电路及其布置方法公开(公告)号：US20060192085A1
公开(公告)日：2006-08-31
申请号：US11341904
申请日：2006-01-27
申请人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
发明人： Georg Eggers , Manfred Proell , Joerg Kliewer , Stephan Schroeder
IPC分类号： H01L31/00
CPC分类号： H01L27/112 , H01L23/5258 , H01L27/105 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.
摘要翻译： 半导体电路包括保险丝和光电元件。 熔丝的导电层至少部分地将光电元件的光电传感器区域从落在半导体电路上的光束遮蔽。 用于半导体电路的熔丝的电光监视的装置还包括用于产生光束的照明装置和连接到半导体电路的两个端子触点的测量装置。 在半导体电路的保险丝的电光监测方法中，测量装置连接到两个端子触点，半导体电路用光束照射。
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公开(公告)号：US06970389B2
公开(公告)日：2005-11-29
申请号：US10757594
申请日：2004-01-15
IPC分类号： G11C11/4097 , G11C7/02
CPC分类号： G11C11/4097 , G11C2207/005
摘要： An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.
摘要翻译： 集成存储器可以包括存储单元阵列，其具有用于选择存储器单元的字线，用于读出或写入存储器单元的数据信号的位线，以及连接到位线对的位线的读出放大器 位线对的末端。 在存储器访问期间的激活状态下，切换到位线对中的一个的至少一个可激活隔离电路可以隔离来自读出放大器更远离读出放大器的位线对的一部分。 结果，在存储器访问期间，可以显着地减少位线的有效电容。
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