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17 条记录 (耗时 0.015 秒)

    MO/TI Contact to silicon
    1.
    发明授权
    MO/TI Contact to silicon 失效
    MO / TI接触硅

    公开(公告)号：US4981816A

    公开(公告)日：1991-01-01

    申请号：US445130

    申请日：1989-11-30

    申请人： Manjin J. Kim ,  Dale M. Brown

    发明人： Manjin J. Kim ,  Dale M. Brown

    IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L21/76855 ,  H01L21/28512 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/02

    摘要： A metal for fabricating contact structures through via openings in VLSI circuits employs a dual layer of refractory metal. A thin titanium layer is deposited, over which a molybdenum layer is formed. An annealing treatment further improves contact resistance characteristics. The method results in a contact structure which exhibits desirable properties of thermal compatibility, step coverage, contact resistance and improved processing characteristics.

    摘要翻译： 用于通过VLSI电路中的通孔开口制造接触结构的金属采用双层难熔金属。 沉积薄的钛层，在其上形成钼层。 退火处理进一步提高了接触电阻特性。 该方法产生显示出所需性质的热相容性，台阶覆盖率，接触电阻和改进的加工特性的接触结构。

    Refractory metal capacitor structures, particularly for analog integrated circuit devices
    4.
    发明授权
    Refractory metal capacitor structures, particularly for analog integrated circuit devices 失效
    耐火金属电容器结构，特别适用于模拟集成电路器件

    公开(公告)号：US4638400A

    公开(公告)日：1987-01-20

    申请号：US790911

    申请日：1985-10-24

    申请人： Dale M. Brown ,  Manjin J. Kim ,  Richard D. Baertsch ,  Thomas L. Vogelsong

    发明人： Dale M. Brown ,  Manjin J. Kim ,  Richard D. Baertsch ,  Thomas L. Vogelsong

    IPC分类号： H01L27/04 ,  H01G4/12 ,  H01G4/33 ,  H01G4/40 ,  H01L21/822 ,  H01L29/92 ,  H01G1/015 ,  B41M3/08 ,  H01L27/02

    CPC分类号： H01L28/40

    摘要： A capacitor structure which is particularly suitable for use in analog integrated circuit devices employs an intermediate layer of a refractory metal disposed in a thin layer overlying a flat dielectric surface. The thinness and the low reflectivity of the refractory metal facilitates precise patterning of the upper plate of the capacitor structure. In the present invention, capacitance is no longer determined by imprecise cuts through thick oxide layers or by patterning of thick metallization layers within these apertures. The use of refractory metals in the capacitor structure also readily permits the incorporation of resistive circuit elements.

    摘要翻译： 特别适用于模拟集成电路器件的电容器结构使用设置在覆盖在平坦电介质表面上的薄层中的难熔金属的中间层。 难熔金属的薄度和低反射率有助于电容器结构的上板的精确图案化。 在本发明中，电容不再通过不精确的切割穿过厚的氧化物层或通过在这些孔内图案化厚的金属化层来确定。 在电容器结构中使用难熔金属也容易地并入电阻电路元件。

    Method of manufacturing a self-aligned vertical bipolar transistor
    7.
    发明授权
    Method of manufacturing a self-aligned vertical bipolar transistor 失效
    制造自对准垂直双极晶体管的方法

    公开(公告)号：US06235601B1

    公开(公告)日：2001-05-22

    申请号：US08934301

    申请日：1997-09-19

    申请人： Manjin J. Kim

    发明人： Manjin J. Kim

    IPC分类号： H01L21331

    CPC分类号： H01L29/66265 ,  Y10S148/01 ,  Y10S148/15

    摘要： A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

    摘要翻译： 阐述了提供自对准的垂直双极晶体管的过程。 提供了一种受控技术，用于提供晶体管的基极和发射极特征，其适当的尺寸和性质可用于高频微波应用。 通过这种技术提供微波晶体管。

    Vertical power MOS device with increased ruggedness and method of fabrication
    8.
    发明授权
    Vertical power MOS device with increased ruggedness and method of fabrication 失效
    垂直功率MOS器件具有增强的耐用性和制造方法

    公开(公告)号：US5268586A

    公开(公告)日：1993-12-07

    申请号：US842853

    申请日：1992-02-25

    申请人： Satyendranath Mukherjee ,  Manjin J. Kim

    发明人： Satyendranath Mukherjee ,  Manjin J. Kim

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

    摘要： A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

    摘要翻译： 提供了一种具有改善的耐用性的半导体器件，其包括在其主表面上具有第一导电类型的区域的半导体衬底; 在所述第一导电类型的区域内选择性地形成相反导电类型的第一基区; 选择性地形成在所述第一基极区内并具有比所述第一基极区更高的杂质浓度的相反导电类型的第二基极区; 在所述第一和第二基极区域内形成并覆盖所述第二基极区域的一种导电类型的源极区域; 以及与沟槽区域相对的多晶硅栅电极，栅极绝缘层插入其间; 其中所述第二基极区域和所述源极区域基本上完全形成在所述第一基极区域内; 所述第二基极区域的深度小于所述第一基极区域，并且形成在足够接近所述沟道区域的距离处，以有效地减小所述第一基极区域中的寄生电阻，所述第二基极区域的侧向边缘基本上与所述侧向 栅电极的边缘; 通过使用多晶硅栅电极作为自对准掩模通过多晶硅栅极电极区域的顺序注入形成第一基极区域和源极区域，然后使用多晶硅栅极电极注入第二基极区域，而不会实质上横向扩散 面具; 并且所述多晶硅栅电极具有足以掩盖所述第一基极区域中所选择的深度植入的厚度。

    Composite conductive structures and method of making same
    9.
    发明授权
    Composite conductive structures and method of making same 失效
    复合导电结构及其制造方法

    公开(公告)号：US4429011A

    公开(公告)日：1984-01-31

    申请号：US362682

    申请日：1982-03-29

    申请人： Manjin J. Kim ,  Tat-Sing P. Chow

    发明人： Manjin J. Kim ,  Tat-Sing P. Chow

    IPC分类号： C23C8/24 ,  H01L21/28 ,  H01L21/318 ,  H01L21/321 ,  B05D5/12 ,  H01L21/306

    CPC分类号： H01L21/28079 ,  C23C8/24 ,  H01L21/28105 ,  H01L21/318 ,  H01L21/321

    摘要： A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of ammonia in the range from about 400.degree. C. to 850.degree. C. for a time to cause the atmosphere to react with the conductor to convert a portion of the conductor into molybdenum nitride.

    摘要翻译： 描述了一种复合导电结构，其包括绝缘基板，其上设置有由氮化钼层覆盖的钼的导体以及制造该结构的方法。 该方法包括在约400℃至850℃的氨气氛中加热钼导体一段时间，使气氛与导体反应，将一部分导体转变为氮化钼。

    Method of producing VDMOS device of increased power density
    10.
    发明授权
    Method of producing VDMOS device of increased power density 失效
    生产增加功率密度的VDMOS器件的方法

    公开(公告)号：US5405794A

    公开(公告)日：1995-04-11

    申请号：US259769

    申请日：1994-06-14

    申请人： Manjin J. Kim

    发明人： Manjin J. Kim

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/126

    摘要： A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

    摘要翻译： 垂直双扩散金属对半导体器件通过一种方法产生，该方法包括通过自对准工艺和剥离工艺形成水平分离的重掺杂Si和源的体，以及形成具有负斜率的沟槽 侧墙。