公开(公告)号：US5151760A

公开(公告)日：1992-09-29

申请号：US738004

申请日：1991-07-30

申请人： Manzur Gill ,  David J. McElroy

发明人： Manzur Gill ,  David J. McElroy

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/7883

摘要： According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and the second conductor (16) is capacitively coupled to third conductor (22).

摘要翻译： 根据本发明，提供了具有改进的电容耦合的集成电路，并且包括第一导体（20），第二导体（16）和第三导体（22）。 第二导体（22）和第三导体（16）彼此相邻设置，由绝缘体区域（60）分开。 第一导体（20）接触第三导体（16）并延伸穿过第三导体（22）的一部分。 第一和第三导体被绝缘体区域（54）隔开。 施加到第一导体（20）和第二导体（16）的电压电容耦合到第三导体（22）。

公开(公告)号：US5523249A

公开(公告)日：1996-06-04

申请号：US364529

申请日：1994-12-23

申请人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

发明人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

摘要翻译： 在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。 福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。 浮动门（13）包括隧道窗部分。 控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。 浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。 通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。 存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除， 。 单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

公开(公告)号：US5110753A

公开(公告)日：1992-05-05

申请号：US576887

申请日：1990-09-04

申请人： Manzur Gill ,  David J. McElroy

发明人： Manzur Gill ,  David J. McElroy

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of progammable memory cells.

摘要翻译： 一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。 位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。 阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。 字线之间和位线之间的隔离是通过厚场氧化物。 字线可以由具有低电阻率的硅化多晶或其它材料形成。 通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。 所得到的结构是可程序记忆单元的密集交叉点阵列。

公开(公告)号：US5334550A

公开(公告)日：1994-08-02

申请号：US4813

申请日：1993-01-15

申请人： David J. McElroy ,  Sung-Wei Lin ,  Manzur Gill

发明人： David J. McElroy ,  Sung-Wei Lin ,  Manzur Gill

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/28 ,  H01L21/308 ,  H01L21/74 ,  H01L21/768 ,  H01L29/423 ,  H01L21/76

CPC分类号： H01L21/76802 ,  H01L21/033 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/743 ,  H01L29/78

摘要： An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semiconductor regions, or may include an electrical conductor connected to a doped semiconductor region, or may include an electrical conductor separated from doped semiconductor regions by an electrical insulator. Embodiments include, but are not limited to, a field-effect transistor, a tunnelling area for a floating gate transistor, and an electrical connection to a doped area of the substrate.

摘要翻译： 在半导体本体的表面上形成的两个绝缘区的凹陷结的自对准窗有关的集成电路结构和工艺。 窗口可以包括在掺杂半导体区域之间形成隔离区域的沟槽，或者可以包括连接到掺杂半导体区域的电导体，或者可以包括通过电绝缘体与掺杂半导体区域分离的电导体。 实施例包括但不限于场效应晶体管，用于浮栅晶体管的隧穿区域以及与衬底的掺杂区域的电连接。

公开(公告)号：US5313432A

公开(公告)日：1994-05-17

申请号：US790122

申请日：1991-11-12

申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

公开(公告)号：US5155055A

公开(公告)日：1992-10-13

申请号：US685358

申请日：1991-04-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US5057446A

公开(公告)日：1991-10-15

申请号：US563369

申请日：1990-08-06

申请人： Manzur Gill ,  David J. McElroy

发明人： Manzur Gill ,  David J. McElroy

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/7883

摘要： According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).

摘要翻译： 根据本发明，提供了具有改进的电容耦合的集成电路，并且包括第一导体（20），第二导体（16）和第三导体（22）。 第二导体（22）和第三导体（16）彼此相邻设置，由绝缘体区域（60）分开。 第一导体（20）接触第三导体（16）并延伸穿过第三导体（22）的一部分。 第一和第三导体被绝缘体区域（54）隔开。 施加到第一导体（20）和第二导体（16）的电压电容耦合到第三导体（22）。

公开(公告)号：US5025494A

公开(公告)日：1991-06-18

申请号：US269838

申请日：1988-11-10

申请人： Manzur Gill ,  David J. McElroy

发明人： Manzur Gill ,  David J. McElroy

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

摘要翻译： 一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。 位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。 阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。 字线之间和位线之间的隔离是通过厚场氧化物。 字线可以由具有低电阻率的硅化多晶或其它材料形成。 通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。 所得到的结构是可编程存储器单元的密集交叉点阵列。

公开(公告)号：US5008721A

公开(公告)日：1991-04-16

申请号：US494042

申请日：1990-03-15

申请人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

发明人： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L29/7883 ,  Y10S257/903

摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

摘要翻译： 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US5177705A

公开(公告)日：1993-01-05

申请号：US402399

申请日：1989-09-05

申请人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

发明人： David J. McElroy ,  Sebastiano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425 ,  G11C16/10

摘要： A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.

摘要翻译： 描述了一种用于编程EEPROM单元阵列的方法。 编程通过位于选定单元的源位线（24）和浮动栅极导体（42）之间的Fowler-Nordheim隧道窗口（34）进行。 选择施加到控制栅极和源极的电压以使其不同以使得电子从源极区域（24）通过隧道窗口（34）从浮动栅极导体（42）拉出。 未选择的位线具有施加在其上的电压，其具有足够的值以防止所选行中的单元的无意编程。 未选择的字线（48）具有其上施加的电压，其具有足够的值以防止编程的未选择单元的擦除。