公开(公告)号：US5313432A

公开(公告)日：1994-05-17

申请号：US790122

申请日：1991-11-12

申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

公开(公告)号：US08174884B2

公开(公告)日：2012-05-08

申请号：US12804395

申请日：2010-07-20

申请人： Harvey J. Stiegler ,  Allan T. Mitchell ,  Robert N. Rountree

发明人： Harvey J. Stiegler ,  Allan T. Mitchell ,  Robert N. Rountree

IPC分类号： G11C11/34

CPC分类号： G11C16/0441

摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).

公开(公告)号：US09042173B2

公开(公告)日：2015-05-26

申请号：US12696766

申请日：2010-01-29

申请人： Harvey J. Stiegler ,  Luan A. Dang

发明人： Harvey J. Stiegler ,  Luan A. Dang

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/02

CPC分类号： G11C7/02 ,  G11C16/04 ,  G11C16/06

摘要： Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.

摘要翻译： 存储架构，例如嵌入在处理器或其他大规模集成电路内的闪存EEPROM存储器，并且包括差分感测电路。 存储器包括行和列中的存储器单元阵列，并且被组织成扇区，每个扇区被分割成部分。 阵列的列被分组成小组，最后一列列解码根据列地址的最低有效位从组中选择一列。 列的相邻组被配对，其中来自每个组的选定的列耦合到读出放大器的差分输入，但是其中一个所选列与未选择的扇区部分相关联，并且因此用作虚拟位线。 通过将未选择的列组保持在选定的列组相邻或附近，导体布线简化，并减少了芯片面积。

公开(公告)号：US20110188311A1

公开(公告)日：2011-08-04

申请号：US12696766

申请日：2010-01-29

申请人： Harvey J. Stiegler ,  Luan A. Dang

发明人： Harvey J. Stiegler ,  Luan A. Dang

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/02

CPC分类号： G11C7/02 ,  G11C16/04 ,  G11C16/06

摘要： Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.

摘要翻译： 存储架构，例如嵌入在处理器或其他大规模集成电路内的闪存EEPROM存储器，并且包括差分感测电路。 存储器包括行和列中的存储器单元阵列，并且被组织成扇区，每个扇区被分割成部分。 阵列的列被分组成小组，最后一列列解码根据列地址的最低有效位从组中选择一列。 列的相邻组被配对，其中来自每个组的选定的列耦合到读出放大器的差分输入，但是其中一个所选列与未选择的扇区部分相关联，并且因此用作虚拟位线。 通过将未选择的列组保持在选定的列组相邻或附近，导体布线简化，并减少了芯片面积。

公开(公告)号：US5786702A

公开(公告)日：1998-07-28

申请号：US565603

申请日：1995-11-30

申请人： Harvey J. Stiegler ,  Steven V. Krzentz

发明人： Harvey J. Stiegler ,  Steven V. Krzentz

IPC分类号： G01R31/28 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： A method for detecting defects between parallel rows of conductors (ROW) in an integrated-circuit array (ARR) includes (a) connecting all alternate rows (ROW) of conductors of the array (ARR) to a first voltage (V.sub.DD) and connecting the other alternate rows (ROW) of conductors of the array (ARR) to a second voltage (V.sub.REF) different from the first voltage, while measuring the current drawn; (b) if the current does not exceed a first limit, ending the process; (c) if the current exceeds the first limit, separately repeating step (a) on first and second halves of the array rather than all of the array, with all of the rows (ROW) of conductors of the half of the array (ARR) not under test connected to the second voltage (V.sub.REF); (d) if the current exceeds a second limit for a half of the array (ARR) in step (c), repeating step (a) on each quarter of the array (ARR) in that half with all of the rows (ROW) of the array (ARR) not under test connected to the second voltage V.sub.REF ; and (e) if the current exceeds a third limit for an array (ARR) quarter in step (d), continuing analogous steps for array (ARR) fractions divisible by two and for predetermined current limits until sufficient information concerning the defects is determined.

摘要翻译： 一种用于检测集成电路阵列（ARR）中的平行导体行（ROW）之间的缺陷的方法包括：（a）将阵列导体（ARR）的所有交替行（ROW）连接到第一电压（VDD）并连接 在测量所绘制的电流的同时，阵列导体（ARR）的其他交替行（ROW）与第一电压不同的第二电压（VREF）; （b）如果当前不超过第一个限制，则结束该过程; （c）如果电流超过第一限制，则在阵列的第一和第二半部分而不是全部阵列上分别重复步骤（a），其中阵列的一半导体（ARR）的所有行（ROW） ）未经测试连接到第二电压（VREF）; （d）如果在步骤（c）中电流超过阵列的一半（ARR）的第二限制，则在所有行（ROW）的该半部中的每个四分之一阵列（ARR）上重复步骤（a） 未测试的阵列（ARR）连接到第二电压VREF; 和（e）如果在步骤（d）中电流超过阵列（ARR）四分之一的第三极限，则连续的阵列（ARR）分数的类似步骤可除以2和预定的电流限制，直到确定有关缺陷的足够的信息为止。

公开(公告)号：US4692638A

公开(公告)日：1987-09-08

申请号：US626576

申请日：1984-07-02

申请人： Harvey J. Stiegler

发明人： Harvey J. Stiegler

IPC分类号： G11C8/08 ,  G11C8/10 ,  H03K19/094

CPC分类号： G11C8/08 ,  G11C8/10

摘要： A decoder and driver circuit for producing an output voltage exceeding the power supply uses a CMOS decode circuit followed by NMOS output stage and pump circuit. The pump clock is derived from a controlled oscillator, and the oscillator is synchronized with the access cycle of the memory device in which the circuit is used, so retention of the high level output is assured for an indefinitely long cycle time.

摘要翻译： 用于产生超过电源的输出电压的解码器和驱动器电路使用CMOS解码电路，随后是NMOS输出级和泵电路。 泵时钟源自受控振荡器，并且振荡器与使用电路的存储器件的访问周期同步，因此保证高电平输出无限期长的周期时间。

公开(公告)号：US08908412B2

公开(公告)日：2014-12-09

申请号：US12804439

申请日：2010-07-20

申请人： Harvey J. Stiegler ,  Allan T. Mitchell

发明人： Harvey J. Stiegler ,  Allan T. Mitchell

IPC分类号： G11C17/00 ,  G11C16/04

CPC分类号： G11C16/0441

摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.

摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储器阵列（图7）。 存储器阵列包括以行和列排列的多个存储单元。 每个存储单元具有开关（714），存取晶体管（716）和感测晶体管（720）。 每个存取晶体管的电流路径与每个相应感测晶体管的电流路径串联连接。 第一程序数据引线（706）连接到第一列中的每个存储器单元的开关。 位线（718）连接到第一列中每个存取晶体管的电流路径。 读取选择引线（721）连接到第一行中的每个存取晶体管的控制端子。 第一行选择引线（700）连接到第一行中的每个存储单元中的开关的控制端子。

公开(公告)号：US20120020163A1

公开(公告)日：2012-01-26

申请号：US12804439

申请日：2010-07-20

申请人： Harvey J. Stiegler ,  Allan T. Mitchell

发明人： Harvey J. Stiegler ,  Allan T. Mitchell

IPC分类号： G11C16/04

CPC分类号： G11C16/0441

摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.

摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储器阵列（图7）。 存储器阵列包括以行和列排列的多个存储单元。 每个存储单元具有开关（714），存取晶体管（716）和感测晶体管（720）。 每个存取晶体管的电流路径与每个相应感测晶体管的电流路径串联连接。 第一程序数据引线（706）连接到第一列中的每个存储器单元的开关。 位线（718）连接到第一列中每个存取晶体管的电流路径。 读取选择引线（721）连接到第一行中的每个存取晶体管的控制端子。 第一行选择引线（700）连接到第一行中的每个存储单元中的开关的控制端子。

公开(公告)号：US20100039868A1

公开(公告)日：2010-02-18

申请号：US12462076

申请日：2009-07-28

申请人： Allan T. Mitchell ,  Harvey J. Stiegler

发明人： Allan T. Mitchell ,  Harvey J. Stiegler

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell (FIGS. 1-2) is disclosed. The memory cell includes a sense transistor (152) having a source (110), a drain (108), and a control gate layer (156). The memory cell includes a first lightly doped region (160) having a first conductivity type and a second lightly doped region (162) having the first conductivity type. A first dielectric region is formed between the control gate layer and the first lightly doped region. A second dielectric region is formed between the control gate layer and the second lightly doped region.

摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储单元（图1-2）。 存储单元包括具有源极（110），漏极（108）和控制栅极层（156）的检测晶体管（152）。 存储单元包括具有第一导电类型的第一轻掺杂区域（160）和具有第一导电类型的第二轻掺杂区域（162）。 在控制栅极层和第一轻掺杂区域之间形成第一电介质区域。 在控制栅极层和第二轻掺杂区域之间形成第二介电区域。

公开(公告)号：US5773997A

公开(公告)日：1998-06-30

申请号：US727842

申请日：1996-10-04

申请人： Harvey J. Stiegler

发明人： Harvey J. Stiegler

IPC分类号： G11C11/413 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C7/06 ,  H03K5/24

CPC分类号： G11C16/28 ,  G11C7/14

摘要： Reference circuitry RC includes a current-sensing translator M5-M7, MX connected to a current reference source RS. The outputs O1, O2, etc. of the current-sensing translator M5-M7, MX are mirrored into one or more sense amplifiers SA1,SA2 of sensing circuitry SC. The current-sensing translator M5-M7, MX permits the current from the current reference source RS to be mirrored to multiple sense amplifiers SA1,SA2 at a predetermined ratio.

摘要翻译： 参考电路RC包括连接到电流参考源RS的电流感测转换器M5-M7，MX。 电流检测转换器M5-M7，MX的输出O1，O2等被镜像到检测电路SC的一个或多个读出放大器SA1，SA2中。 电流检测转换器M5-M7，MX允许来自当前参考源RS的电流以预定比例被镜像到多个读出放大器SA1，SA2。