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1.发明授权Segmented, multiple-decoder memory array and method for programming a memory array 失效分段的多解码器存储器阵列和用于编程存储器阵列的方法
公开(公告)号：US5313432A
公开(公告)日：1994-05-17
申请号：US790122
申请日：1991-11-12
申请人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
发明人： Sung-Wei Lin , John F. Schreck , Phat C. Truong , David J. McElroy , Harvey J. Stiegler , Benjamin H. Ashmore, Jr. , Manzur Gill
CPC分类号： G11C16/0416 , G11C16/08 , G11C16/12 , G11C5/025 , G11C8/12
摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。
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2.发明授权Nonvolatile memory array wordline driver circuit with voltage translator circuit 失效具有电压转换电路的非易失性存储器阵列字线驱动电路
公开(公告)号：US5287536A
公开(公告)日：1994-02-15
申请号：US9276
申请日：1993-01-22
摘要： A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed.
摘要翻译： 用于驱动浮栅型EEPROM单元阵列中的字线或字线组的电路包括用于切换正读取电压的读取驱动器子电路，用于切换正编程电压的程序驱动器子电路和可选地用于切换负极的子电路 擦除电压。 当连接到高电容字线时，读驱动器子电路可以使用相对较短的沟道晶体管来构造，用于相对高速的操作。 另一方面，程序驱动器子电路可以使用相对长的沟道晶体管构成，并且那些长沟道晶体管可以远离存储器单元和读取驱动器电路位于存储器芯片上。 P沟道隔离晶体管用于在运行期间隔离未使用的电路。 程序驱动器子电路中的电压转换器具有减小超过这些晶体管的击穿电压的可能性的晶体管配置。 还公开了非易失性存储单元阵列的编程方法。
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公开(公告)号：US07069485B2
公开(公告)日：2006-06-27
申请号：US10695606
申请日：2003-10-28
IPC分类号： G01R31/3158
CPC分类号： G01R31/318572 , G11C29/32 , G11C29/48 , G11C2029/3202
摘要： A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations operations.
摘要翻译： 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路中，使得可以将串行数据写入存储器并从存储器写入，而不必重复地循环通过多个TAP读取或写入操作操作。
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公开(公告)号：US06675333B1
公开(公告)日：2004-01-06
申请号：US09718206
申请日：2000-11-21
IPC分类号： G01R313185
CPC分类号： G01R31/318572 , G11C29/32 , G11C29/48 , G11C2029/3202
摘要： A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
摘要翻译： 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路上，使得串行数据可以被写入存储器并从存储器写入，而不必重复地循环通过多个移位操作。
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公开(公告)号：US5687179A
公开(公告)日：1997-11-11
申请号：US415121
申请日：1995-03-29
IPC分类号： G06F13/38 , G01R31/3185 , G11C29/32
CPC分类号： G01R31/318558 , G11C29/32
摘要： A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
摘要翻译： 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路上，使得串行数据可以被写入存储器并从存储器写入，而不必重复地循环通过多个移位操作。
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公开(公告)号：US5491660A
公开(公告)日：1996-02-13
申请号：US341733
申请日：1994-11-18
摘要： The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder (MID), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and an optional subroutine stack (SS) to allow function calls. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.
摘要翻译： 本发明的存储器控制包括包含用于集成电路存储器的操作的微指令的微程序只读存储器（CROM），用于从控制只读存储器选择指令的程序计数器多路复用器（PCM） 微指令解码器（MID），用于测试控制信号的测试输入多路复用器（TIM），用于产生控制信号的可选状态输出寄存器（SOR）和用于允许功能调用的可选子程序堆栈（SS）。 集成电路存储器的复杂程序，擦除和压缩指令使用相对较少数量的控制只读存储器位置并使用存储器芯片上相对较小的表面积来实现。 控制指令易于修改以补偿在集成电路存储器的生产寿命期间进行的处理和结构增强。
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公开(公告)号：US5267204A
公开(公告)日：1993-11-30
申请号：US780685
申请日：1991-10-18
摘要： A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.
摘要翻译： 提供了一种用于掩蔽存储器设备中的数据的方法和电路，其检测存储器件内的至少一个故障位位置是否等于输入数据内的相应位。 根据失败的位位置是否等于对应的位，将数据从输入数据中选择性地反转写入存储器件。 选择性地设置存储器件内的反转位以指示写入的数据是否从输入数据反转。
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公开(公告)号：US08228220B2
公开(公告)日：2012-07-24
申请号：US13099665
申请日：2011-05-03
IPC分类号： H03M1/10
摘要： Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
摘要翻译： 公开了用于操作转换器或其它电路的方法，系统和装置。 更具体地，在一个实施例中，转换器或其他电路可以以两种模式操作，这两种模式可以包括计数到时间和时间计数模式以确定对应于输入信号的输出值。 在计数到时间模式的操作期间，可以使用参考信号来操作转换器，以确定所需的时钟周期数，直到输出对应于缩放因子为止。 在时间到计数模式下的电路操作期间，转换器可以使用输入信号来操作这个数量的时钟周期，以确定输出。 该输出可能与输入信号上的电平成比例。
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公开(公告)号：US5132935A
公开(公告)日：1992-07-21
申请号：US509532
申请日：1990-04-16
CPC分类号： G11C16/3477 , G11C16/10 , G11C16/14 , G11C16/3409 , G11C16/3468
摘要： The device and process of this invention provide for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages, decreasing the energy-level of each of the alternating erasing and programming voltages. The initial, relatively high-energy-level pulses should have sufficient energy to cause all of the cells to be programmed and to cause all of the cells to be over-erased. The energy-levels are decreased until electron transfer between floating gate and a source or drain region ceases. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted. The final threshold voltages are distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage.
摘要翻译： 本发明的装置和方法提供了通过随后向EEPROM阵列的单元施加交替的擦除和编程脉冲来消除由过擦除的单元导致的读取误差，从相对高能量级的擦除和编程电压开始，从而降低能量 每个交流擦除和编程电压的电平。 初始的相对高能级的脉冲应该具有足够的能量以使得所有的单元被编程并且使得所有的单元被过度擦除。 能量水平降低，直到浮栅和源极或漏极区之间的电子转移停止。 随着能量的降低，存储单元的阈值电压范围被压缩。 最终阈值电压分布在小于预定字线选择电压的正值的预选窄范围内。
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公开(公告)号：US5010522A
公开(公告)日：1991-04-23
申请号：US443293
申请日：1989-11-29
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/103
摘要： An integrated-circuit memory-array configuration for providing less total access time when used in conjunction with a microprocessor. The configuration includes a line buffer with perhaps 256 latches for storing data, and first and second pipeline circuits for sensing linearity and locality of access information pertaining to the requested data. When used with a microprocessor that is programmed with repeated requests for the same data, a majority of the data requests will be transmitted quickly from the line buffer. If the data requests are not in the line buffer, the configuration furnishes a signal to the microprocessor and the requested data are moved from the floating-gate memory cell array to the line buffer for subsequent transmittal to the microprocessor.
摘要翻译： 集成电路存储器阵列配置，用于在与微处理器结合使用时提供更少的总访问时间。 该配置包括具有用于存储数据的256个锁存器的行缓冲器，以及用于感测与所请求数据有关的访问信息的线性和位置的第一和第二流水线电路。 当与与相同数据的重复请求编程的微处理器一起使用时，大部分数据请求将从行缓冲区快速传输。 如果数据请求不在行缓冲器中，则配置向微处理器提供信号，并且所请求的数据从浮栅存储器单元阵列移动到行缓冲器，以便随后传送到微处理器。
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