公开(公告)号：US5313432A

公开(公告)日：1994-05-17

申请号：US790122

申请日：1991-11-12

申请人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

发明人： Sung-Wei Lin ,  John F. Schreck ,  Phat C. Truong ,  David J. McElroy ,  Harvey J. Stiegler ,  Benjamin H. Ashmore, Jr. ,  Manzur Gill

IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/06

CPC分类号： G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C5/025 ,  G11C8/12

摘要： A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

摘要翻译： 非易失性存储器阵列的字线解码系统被分成三个较小的解码子系统（读模式解码子系统，程序/擦除模式解码子系统和段选择解码器子系统）。 分段阵列具有小的位线电容，并且需要几个输入连接到每个解码子系统。 读模式解码器电路和编程/擦除模式解码器电路分开，允许读模式解码器电路用于高速访问，并允许对高电压操作进行编程/擦除模式解码器电路。 掩埋位线段选择晶体管减少了那些晶体管所需的面积。 可以在首先检查段的每一行以确定任何过度擦除的单元的存在之后执行擦除。 可以通过允许所选段的公共源列线浮动并且将预选的电压放置在适当的字线和漏极 - 列线上来执行编程。

公开(公告)号：US5287536A

公开(公告)日：1994-02-15

申请号：US9276

申请日：1993-01-22

申请人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

发明人： John F. Schreck ,  Phat C. Truong ,  Benjamin H. Ashmore, Jr. ,  Harvey J. Steigler

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/06 ,  G11C5/14

CPC分类号： G11C16/08 ,  G11C16/12

摘要： A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded. A method for programming nonvolatile memory cell arrays is also disclosed.

摘要翻译： 用于驱动浮栅型EEPROM单元阵列中的字线或字线组的电路包括用于切换正读取电压的读取驱动器子电路，用于切换正编程电压的程序驱动器子电路和可选地用于切换负极的子电路 擦除电压。 当连接到高电容字线时，读驱动器子电路可以使用相对较短的沟道晶体管来构造，用于相对高速的操作。 另一方面，程序驱动器子电路可以使用相对长的沟道晶体管构成，并且那些长沟道晶体管可以远离存储器单元和读取驱动器电路位于存储器芯片上。 P沟道隔离晶体管用于在运行期间隔离未使用的电路。 程序驱动器子电路中的电压转换器具有减小超过这些晶体管的击穿电压的可能性的晶体管配置。 还公开了非易失性存储单元阵列的编程方法。

公开(公告)号：US5140554A

公开(公告)日：1992-08-18

申请号：US574835

申请日：1990-08-30

申请人： John F. Schreck ,  Phat C. Truong ,  David Tatman

发明人： John F. Schreck ,  Phat C. Truong ,  David Tatman

IPC分类号： G11C17/18 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50008 ,  G01R31/31702 ,  G11C16/04

摘要： A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.

摘要翻译： 用于确定集成电路的熔丝线是否已经由例如激光装置正确地打开或闭合的测试电路。 在一个实施例中，本发明的测试电路包括连接在电压源和输出端之间的可变阻抗，例如P沟道晶体管，该阻抗具有一个值，第一输入端施加到可变阻抗控制端 并且响应于施加到可变阻抗控制端子的第二输入而具有第二较大的值。 在输出端子和参考电位源之间串联连接至少一个可编程熔丝管和栅极。 用于向可变阻抗提供控制输入的装置连接在测试模式输入信号和可变阻抗的控制端之间。 用于向P沟道晶体管提供控制输入的装置可以包括第二电流镜连接的P沟道晶体管。

公开(公告)号：US5636226A

公开(公告)日：1997-06-03

申请号：US369978

申请日：1995-01-09

申请人： Phat C. Truong ,  John F. Schreck

发明人： Phat C. Truong ,  John F. Schreck

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G01R31/318525 ,  G11C29/02 ,  G11C29/022 ,  G01R31/002 ,  G01R31/31816 ,  G11C11/41

摘要： A fault sensing circuit for detecting the state of at least one latch controlled by at least one control signal is provided. The circuit comprises an additional latch also controlled by the same control signal and receiving an input of a known value. The output of the additional latch is coupled to an I/O pin where an external circuit may monitor its logic state to determine the occurrence of a fault.

摘要翻译： 提供一种用于检测由至少一个控制信号控制的至少一个锁存器的状态的故障感测电路。 电路还包括一个附加的锁存器，它也由相同的控制信号控制，并接收一个已知值的输入。 附加锁存器的输出耦合到I / O引脚，其中外部电路可以监视其逻辑状态以确定故障的发生。

公开(公告)号：US5197029A

公开(公告)日：1993-03-23

申请号：US651817

申请日：1991-02-07

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

CPC分类号： G11C16/30

摘要： A common connection to reduces the amount of chip area required to perform read and programming functions, particularly where signals such as read, programming, supply voltage and data signals are generated from remote locations on the memory chip. The common connection is made in an integrated circuit having a control circuit, a plurality of memory cell arrays having column lines, a sense amplifier circuit, and a programming circuit including at least first and second parts. At least one column of one memory cell array is selectively connected to a common line/node upon receiving at least a first signal from the control circuit. The first part of the programming circuit is selectively connected to the common line/node upon receiving a second signal from the control circuit. The second part of the programming circuit is connected to the common line/node upon receiving a third signal from the control circuit. The sense amplifier circuit is selectively connected to the common line/node upon receiving a fourth signal from the control circuit. The common line/node may be a conductor extending from a first area of the integrated-circuit memory to a second area of the integrated-circuit memory, the first and second areas including, for example, the first and second parts of the programming circuit respectively located at opposite ends of the integrated-circuit memory. The first part of the programming circuit may provide a high voltage to a source-column line of the integrated-circuit memory. The second part of the programming circuit may provide a reference potential and a supply voltage to the common line/node.

公开(公告)号：US5491658A

公开(公告)日：1996-02-13

申请号：US655566

申请日：1991-02-13

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C17/00

CPC分类号： G11C16/08 ,  G11C8/10 ,  G11C8/12

摘要： A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.

摘要翻译： 虚拟接地存储器包括存储器单元的行和列的阵列以及多个交替的第一和第二列线。 每列中的单元被耦合到第一列线和第二列线。 第一解码器响应于第一解码地址信号选择多个第一列线，并且响应于第二解码地址信号选择所选择的多个第一列线中的一个。

公开(公告)号：US5182726A

公开(公告)日：1993-01-26

申请号：US645078

申请日：1991-01-23

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C7/12 ,  G11C16/26

CPC分类号： G11C7/12 ,  G11C16/26

摘要： A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit. The common node may be coupled to the gate of the driver transistor by a coupling transistor having a source-drain path connected between the common node and the gate of the driver transistor and a gate connected to a virtual ground signal.

摘要翻译： 一种用于从存储器阵列的排列列线路快速去除排列编程电压的电路和方法。 电路包括连接在电源电压和公共节点之间的电阻/晶体管，电阻/晶体管由程序使能信号使能。 在放电操作期间，阵列的驱动器晶体管的源极 - 漏极路径将列线连接到参考电位。 驱动器晶体管的栅极耦合到公共节点。 启用晶体管具有将参考电位连接到公共节点的源极 - 漏极路径，并且具有连接到编程使能信号的栅极。 该电路包括至少一个反相器，或电路和旁路晶体管。 旁路晶体管具有连接在电源电压和公共节点之间的源极 - 漏极路径，以及通过反相器和OR电路耦合到公共节点的栅极。 公共节点可以通过耦合晶体管耦合到驱动晶体管的栅极，耦合晶体管具有连接在驱动晶体管的公共节点和栅极之间的源极 - 漏极路径，以及连接到虚拟接地信号的栅极。

公开(公告)号：US5132933A

公开(公告)日：1992-07-21

申请号：US631606

申请日：1990-12-21

申请人： John F. Schreck ,  Shailesh R. Kadakia ,  Phat C. Truong

发明人： John F. Schreck ,  Shailesh R. Kadakia ,  Phat C. Truong

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26

CPC分类号： G11C7/12 ,  G11C16/26

摘要： A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline. The circuit includes a common node; a resistor means coupled between the common node and each of the source- and drain-column lines; a drain-select means coupled to each drain-column line for transmitting, during a read cycle, a first preselected bias voltage lower than a supply voltage to the selected drain-column line; a source-select means coupled to each source-column line for transmitting, during the read cycle, a second preselected bias voltage to the one non-selected source-column line, the one non-selected source-column line coupled to a cell sharing the selected drain-column line and the selected wordline; and reference-select means for connecting, during the read cycle, the source-column lines, except the one non-selected source-column line, to reference potential. The sense amplifier and the driver circuit each include at least three transistors and have outputs coupled to drain-column lines and source-column lines, respectively, of the memory array.

摘要翻译： 一种偏置电路，用于读取半导体存储器单元阵列的选定单元，其中每个单元耦合到漏 - 列线，源列线和字线，所选择的单元耦合到选定的漏 - 列线， 选择的源列行和选定的字线。 该电路包括一个公共节点; 耦合在公共节点和源极 - 漏极列线路中的每一个之间的电阻器件; 耦合到每个漏 - 列线的漏极选择装置，用于在读周期期间将低于供给电压的第一预选偏压电压传送到所选择的漏 - 列线; 耦合到每个源极列线的源极选择装置，用于在读取周期期间将第二预选偏置电压发送到所述一个未选择的源极列线，所述一个未选择的源极线耦合到一个小区共享 所选择的排列列线和所选择的字线; 以及参考选择装置，用于在读取周期期间将除了一个未选择的源列线之外的源极列线连接到参考电位。 读出放大器和驱动电路各自包括至少三个晶体管，并且具有分别耦合到存储器阵列的漏 - 列线和源 - 列线的输出。

公开(公告)号：US5022008A

公开(公告)日：1991-06-04

申请号：US450711

申请日：1989-12-14

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C17/00 ,  G11C16/34 ,  G11C29/00 ,  G11C29/56

CPC分类号： G11C16/34

摘要： A method for measuring the access time or speed of PROM devices is described. The PROM (10) includes a matrix of erased memory cells (30-70) each selectable by an address, and readable by a sense amplifier (112). The method comprises providing an invalid address and reading the level at the sense amplifier (112). A valid address is then provided, and the memory cell addressed is read. The above steps are repeated until all memory cells are read. In this manner, the time required to access an erased memory cell after accessing a programmed memory cell, as simulated by a nonexistent memory cell, may be measured.

公开(公告)号：US5020026A

公开(公告)日：1991-05-28

申请号：US450702

申请日：1989-12-14

申请人： John F. Schreck ,  Phat C. Truong

发明人： John F. Schreck ,  Phat C. Truong

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C16/26

摘要： Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.