公开(公告)号：US20180091437A1

公开(公告)日：2018-03-29

申请号：US15274715

申请日：2016-09-23

申请人： Mario Flajslik ,  Gene Wu ,  Michael A. Parker

发明人： Mario Flajslik ,  Gene Wu ,  Michael A. Parker

IPC分类号： H04L12/927 ,  H04L12/741 ,  H04L12/24

CPC分类号： H04L47/803 ,  H04L41/0893 ,  H04L41/0896 ,  H04L45/745 ,  H04L49/1515

摘要： Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.

公开(公告)号：US20090011543A1

公开(公告)日：2009-01-08

申请号：US11773277

申请日：2007-07-03

申请人： Tjandra Winata Karta ,  Steven Hsu ,  Chien-Hsiun Lee ,  Gene Wu ,  Jimmy Liang

发明人： Tjandra Winata Karta ,  Steven Hsu ,  Chien-Hsiun Lee ,  Gene Wu ,  Jimmy Liang

IPC分类号： H01L21/00

CPC分类号： H01L23/3178 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11

摘要： An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.

摘要翻译： 描述了改进的晶片级芯片级封装（WLCSP）工艺，其包括在半导体晶片的第一表面上形成多个导电柱。 将一个或多个凹槽干蚀刻到半导体晶片的第一表面中，其中凹槽限定半导体晶片内的多个裸片中的每一个之间的至少一个边界。 一层封装材料沉积在第一表面上。 然后通过封装材料在每个凹槽中切割凹部，其中切割在半导体晶片的第二表面上留下一片半导体材料。 然后将第二表面研磨以去除该半导体材料片，其中该材料的去除分离多个管芯。

公开(公告)号：US20080131996A1

公开(公告)日：2008-06-05

申请号：US11633718

申请日：2006-12-05

申请人： Gene Wu

发明人： Gene Wu

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4846 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H05K3/205 ,  H05K3/3473 ,  H05K2201/09745 ,  H05K2201/10674 ,  H01L2224/0401

摘要： A reverse build-up method for forming a package substrate includes forming bumps; forming an interconnect structure connected to the bumps; and forming ball grid array (BGA) balls on the interconnect structure. The BGA balls are electrically connected to the bumps through the interconnect structure. The step of forming the bumps are performed before the steps of forming the interconnect structure and forming the BGA balls.

摘要翻译： 用于形成封装衬底的反向堆叠方法包括形成凸块; 形成连接到所述凸块的互连结构; 并在互连结构上形成球栅阵列（BGA）球。 BGA球通过互连结构电连接到凸块。 形成凸块的步骤在形成互连结构并形成BGA球的步骤之前进行。

公开(公告)号：US07838424B2

公开(公告)日：2010-11-23

申请号：US11773277

申请日：2007-07-03

申请人： Tjandra Winata Karta ,  Steven Hsu ,  Chien-Hsiun Lee ,  Gene Wu ,  Jimmy Liang

发明人： Tjandra Winata Karta ,  Steven Hsu ,  Chien-Hsiun Lee ,  Gene Wu ,  Jimmy Liang

IPC分类号： H01L21/302

CPC分类号： H01L23/3178 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10157 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11

摘要： An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.

摘要翻译： 描述了改进的晶片级芯片级封装（WLCSP）工艺，其包括在半导体晶片的第一表面上形成多个导电柱。 将一个或多个凹槽干蚀刻到半导体晶片的第一表面中，其中凹槽限定半导体晶片内的多个裸片中的每一个之间的至少一个边界。 一层封装材料沉积在第一表面上。 然后通过封装材料在每个凹槽中切割凹部，其中切割在半导体晶片的第二表面上留下一片半导体材料。 然后将第二表面研磨以去除该半导体材料片，其中该材料的去除分离多个管芯。

公开(公告)号：US07642129B2

公开(公告)日：2010-01-05

申请号：US11648926

申请日：2007-01-03

申请人： Jimmy Liang ,  Gene Wu ,  Steven Hsu

发明人： Jimmy Liang ,  Gene Wu ,  Steven Hsu

IPC分类号： H01L21/00

CPC分类号： H05K3/3457 ,  H01L21/4853 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2203/0278 ,  H05K2203/043

摘要： A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.

摘要翻译： 提供一种形成包装结构的方法及其形成的包装。 该方法包括提供具有顶表面的封装并将焊球放置在封装的顶表面上。 然后将共面表面放置在焊球上，其中该表面是非粘合的。 对焊球进行回流处理，使得焊球的顶表面基本上共面。 然后去除共面。

公开(公告)号：US20080099912A1

公开(公告)日：2008-05-01

申请号：US11588481

申请日：2006-10-27

申请人： Gene Wu

发明人： Gene Wu

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L23/142 ,  H01L23/49866 ,  H01L23/562 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.

摘要翻译： 提供半导体封装结构。 该结构包括包含合金42的基层; 模具附接在基层的第一侧上; 以及在管芯上的互连结构，其中互连结构包括通孔和连接到管芯的导线。

公开(公告)号：US07830004B2

公开(公告)日：2010-11-09

申请号：US11588481

申请日：2006-10-27

申请人： Gene Wu

发明人： Gene Wu

IPC分类号： H01L23/06 ,  H01L23/14

CPC分类号： H01L23/5389 ,  H01L23/142 ,  H01L23/49866 ,  H01L23/562 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor packaging structure is provided. The structure includes a base layer comprising alloy 42; die attached on a first side of the base layer; and an interconnect structure on the die, wherein the interconnect structure comprises vias and conductive lines connected to the die.

摘要翻译： 提供半导体封装结构。 该结构包括包含合金42的基层; 模具附接在基层的第一侧上; 以及在管芯上的互连结构，其中互连结构包括通孔和连接到管芯的导线。

公开(公告)号：US20080160671A1

公开(公告)日：2008-07-03

申请号：US11648926

申请日：2007-01-03

申请人： Jimmy Liang ,  Gene Wu ,  Steven Hsu

发明人： Jimmy Liang ,  Gene Wu ,  Steven Hsu

IPC分类号： H01L21/70

CPC分类号： H05K3/3457 ,  H01L21/4853 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2203/0278 ,  H05K2203/043

摘要： A method of forming a packaging structure and the packages formed thereof are provided. The method includes providing a package having a top surface and placing solder balls on the top surface of the package. A coplanar surface is then placed against the solder balls, wherein the surface is non-adhesive. A reflow process is performed to the solder balls, so that top surfaces of the solder balls are substantially coplanar. The coplanar surface is then removed.

摘要翻译： 提供一种形成包装结构的方法及其形成的包装。 该方法包括提供具有顶表面的封装并将焊球放置在封装的顶表面上。 然后将共面表面放置在焊球上，其中该表面是非粘合的。 对焊球进行回流处理，使得焊球的顶表面基本上共面。 然后去除共面。