公开(公告)号：US20110127880A1

公开(公告)日：2011-06-02

申请号：US12629629

申请日：2009-12-02

申请人： Mark J. Murphy ,  Alan Gillespie ,  Eoin Edward English ,  Donal Geraghty ,  Dennis A. Dempsey

发明人： Mark J. Murphy ,  Alan Gillespie ,  Eoin Edward English ,  Donal Geraghty ,  Dennis A. Dempsey

IPC分类号： H01L41/09

CPC分类号： H01L41/042

摘要： A device and method are provided to drive piezoelectric elements in haptic applications. In one embodiment, a pattern generator provides user programmable PWM waveforms to a driver. The load of the driver is an inductor in series with the piezoelectric element. The filtration of the inductor in series with the capacitance of the piezoelectric element suppresses the high-frequency components of the PWM pulse train, and recovers a value commensurate with the duty cycle of the PWM pulse train. The resulting waveform across the piezoelectric element is converted to physical motion, thereby creating a haptic effect on a user interface. Advantageously, there is reduced power loss, reduced switching induced noise, and a more haptic rich environment.

摘要翻译： 提供了一种在触觉应用中驱动压电元件的装置和方法。 在一个实施例中，模式发生器向驱动器提供用户可编程的PWM波形。 驱动器的负载是与压电元件串联的电感器。 与压电元件的电容串联的电感器的过滤抑制了PWM脉冲串的高频分量，并且恢复与PWM脉冲串的占空比相当的值。 将压电元件的结果波形转换为物理运动，从而在用户界面上产生触觉效果。 有利地，减少了功率损耗，降低了开关感应噪声，并且更有触觉丰富的环境。

公开(公告)号：US08305200B2

公开(公告)日：2012-11-06

申请号：US12629629

申请日：2009-12-02

申请人： Mark J. Murphy ,  Alan Gillespie ,  Eoin Edward English ,  Donal Geraghty ,  Dennis A. Dempsey

发明人： Mark J. Murphy ,  Alan Gillespie ,  Eoin Edward English ,  Donal Geraghty ,  Dennis A. Dempsey

IPC分类号： H04B3/36

CPC分类号： H01L41/042

摘要： A device and method are provided to drive piezoelectric elements in haptic applications. In one embodiment, a pattern generator provides user programmable PWM waveforms to a driver. The load of the driver is an inductor in series with the piezoelectric element. The filtration of the inductor in series with the capacitance of the piezoelectric element suppresses the high-frequency components of the PWM pulse train, and recovers a value commensurate with the duty cycle of the PWM pulse train. The resulting waveform across the piezoelectric element is converted to physical motion, thereby creating a haptic effect on a user interface. Advantageously, there is reduced power loss, reduced switching induced noise, and a more haptic rich environment.

摘要翻译： 提供了一种在触觉应用中驱动压电元件的装置和方法。 在一个实施例中，模式发生器向驱动器提供用户可编程的PWM波形。 驱动器的负载是与压电元件串联的电感器。 与压电元件的电容串联的电感器的过滤抑制了PWM脉冲串的高频分量，并且恢复与PWM脉冲串的占空比相当的值。 将压电元件的结果波形转换为物理运动，从而在用户界面上产生触觉效果。 有利地，减少了功率损耗，降低了开关感应噪声，并且更有触觉丰富的环境。

公开(公告)号：US08659349B1

公开(公告)日：2014-02-25

申请号：US13626630

申请日：2012-09-25

申请人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

发明人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

IPC分类号： G06G7/12

CPC分类号： G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

摘要： A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

摘要翻译： 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1的零传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2pi弧度或其倍数，其中N大于1。

公开(公告)号：US20080265860A1

公开(公告)日：2008-10-30

申请号：US11796964

申请日：2007-04-30

申请人： Dennis A. Dempsey ,  Stefan Marinca

发明人： Dennis A. Dempsey ,  Stefan Marinca

IPC分类号： G05F3/20

CPC分类号： G05F3/30

摘要： A bandgap voltage reference circuit is described. By providing first and second bipolar devices that are operable with different current densities a base emitter voltage difference is created. This voltage difference is increased by coupling first and second cascode circuits to the first and second bipolars, the cascode circuits also being scaled relative to one another.

摘要翻译： 描述带隙电压参考电路。 通过提供可在不同电流密度下操作的第一和第二双极器件，产生基极发射极电压差。 通过将第一和第二共源共栅电路耦合到第一和第二双极来增加该电压差，共源共栅电路也相对于彼此缩放。

公开(公告)号：US08912940B2

公开(公告)日：2014-12-16

申请号：US13841150

申请日：2013-03-15

申请人： Dennis A. Dempsey

发明人： Dennis A. Dempsey

IPC分类号： H03M1/78 ,  H03M1/08 ,  H03M1/68 ,  H03M1/76

CPC分类号： H03M1/0872 ,  H03M1/682 ,  H03M1/765

摘要： Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

摘要翻译： 本发明的实施例可以提供具有电荷增压的串联DAC。 串DAC可以包括多个串，例如MSB DAC和LSB DAC，用于将数字字转换成相应的模拟电压。 串DAC还可以包括充电提升系统，以在诸如MSB代码转换的代码转换期间将电荷耦合到DAC中或从DAC中耦合。 串DAC可以在制造前连接技术中进行操作，其中在进行新连接之前所有相关连接基本上都是开路的。 因此，充电提升可以缩短代码转换之间的串DAC中的阻抗元件的建立时间，并且可以显着地减少（或消除）毛刺。

公开(公告)号：US07339508B2

公开(公告)日：2008-03-04

申请号：US11474174

申请日：2006-06-23

申请人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

发明人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

IPC分类号： H03M1/06

CPC分类号： H03M1/1038 ,  H03M1/662 ,  H03M1/68

摘要： The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

摘要翻译： 本发明提供一种多通道DAC电路，其提供多个通道中的选定的通道之间的相关性，使得可以使用单组校准系数来校准多个通道。

公开(公告)号：US06823416B1

公开(公告)日：2004-11-23

申请号：US09837659

申请日：2001-04-18

申请人： Dennis A. Dempsey ,  Thomas G. O'Dwyer ,  Oliver James Brennan ,  Helen Stapleton ,  Alan Walsh ,  Tudor Vinereanu

发明人： Dennis A. Dempsey ,  Thomas G. O'Dwyer ,  Oliver James Brennan ,  Helen Stapleton ,  Alan Walsh ,  Tudor Vinereanu

IPC分类号： G06F1300

CPC分类号： H03M1/662

摘要： A method for communicating between a controller and a device with double-buffered inputs comprises the steps of providing one or more communication paths for exchanging data between the controller and the device, providing a data transfer control signal from the controller to the device for transferring input data from one or more input registers into one or more latchable data registers, and providing a data transfer delay signal from the device to the controller, wherein, in a first logic state, the data transfer delay signal prevents transfer of input data from the input registers into the latchable data registers until after a transition to a second logic state occurs on the data transfer delay signal. An apparatus for communicating between a controller and a device is also described.

摘要翻译： 一种用于在具有双缓冲输入的控制器和设备之间进行通信的方法包括以下步骤：提供用于在控制器和设备之间交换数据的一个或多个通信路径，从控制器向设备提供数据传输控制信号以传送输入 从一个或多个输入寄存器到一个或多个可锁定数据寄存器的数据，以及从该设备向控制器提供数据传输延迟信号，其中在第一逻辑状态下，数据传输延迟信号防止输入数据从输入 注册到可锁存数据寄存器中，直到在数据传输延迟信号上发生转换到第二逻辑状态。 还描述了用于在控制器和设备之间进行通信的装置。

公开(公告)号：US20180323798A1

公开(公告)日：2018-11-08

申请号：US15947222

申请日：2018-04-06

申请人： Tony Yincai Liu ,  Dennis A. Dempsey

发明人： Tony Yincai Liu ,  Dennis A. Dempsey

IPC分类号： H03M1/78 ,  H03M1/08 ,  H03M1/70 ,  H03M1/76 ,  H03M1/68 ,  H03M1/10 ,  G05D3/14

CPC分类号： H03M1/808 ,  G05D3/1436 ,  H03M1/08 ,  H03M1/1057 ,  H03M1/68 ,  H03M1/682 ,  H03M1/70 ,  H03M1/765 ,  H03M1/785

摘要： Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

公开(公告)号：US09124296B2

公开(公告)日：2015-09-01

申请号：US13841516

申请日：2013-03-15

申请人： Dennis A. Dempsey

发明人： Dennis A. Dempsey

IPC分类号： H03M1/78 ,  H03M1/66 ,  H03M1/10 ,  H03M1/68 ,  H03M1/76

CPC分类号： H03M1/66 ,  H03M1/1061 ,  H03M1/682 ,  H03M1/765

摘要： Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

摘要翻译： 本发明的实施例可以提供具有用于有效分辨率扩展的多个级的串DAC架构。 第一级可以包括阻抗串（例如，电阻串）。 第二级可以包括具有多于两个状态（阻抗值）的每个开关的开关网络。 第三级可以包括具有一组相应开关的阻抗串的串DAC。 在多通道实施例中，可以为每个通道提供多个第二和第三级，同时共享相同的第一级（即，阻抗串）。 可以基于诸如MSB值之类的不同信道之间的关系来控制每个第二级交换机网络。 因此，第二级开关网络可以提供不同的阻抗值来补偿多通道，多级串型DAC设计中的负载效应。

公开(公告)号：US06414616B1

公开(公告)日：2002-07-02

申请号：US09602100

申请日：2000-06-22

申请人： Dennis A. Dempsey

发明人： Dennis A. Dempsey

IPC分类号： H03M178

CPC分类号： H03M1/682 ,  H03M1/765

摘要： An improved voltage scaling DAC responsive to an N-bit input code word having M LSBs including first and second outer impedance string segments, each comprising 2N−M−1 series-connected impedances of substantially equal value, an inner string of series-connected impedances of substantially equal value having first and second end points, first and second outer string switch networks providing electrical connections between selected outer string impedance terminals and first and second common nodes, and an inner string switch network providing electrical connection between selected inner string impedance terminals and an output node. The inner string of series-connected impedances comprises no more than 2M−1 impedances of substantially equal value. A method for adjusting the gain of a voltage scaling DAC is also described.

摘要翻译： 响应于具有M个LSB的N位输入码字的改进的电压缩放DAC，每个LSB包括第一和第二外部阻抗串段，每个包括基本相等的2N-M-1个串联连接的阻抗，串联连接的阻抗 具有第一和第二端点的基本相等的值，第一和第二外部串开关网络，其提供所选择的外部串联阻抗端子与第一和第二公共节点之间的电连接;以及内部串开关网络，其提供所选择的内部串阻抗端子与 输出节点。 串联的阻抗的内串包括不大于相等值的2M-1阻抗。 还描述了一种用于调整电压缩放DAC的增益的方法。