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    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance
    1.
    发明授权
    Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
    制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法

    公开(公告)号：US06855608B1

    公开(公告)日：2005-02-15

    申请号：US10463643

    申请日：2003-06-17

    申请人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    发明人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/11573

    摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

    摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间​​露出衬底，并且在其上制造导体以增强每个位线的导电性。

    Recessed channel
    4.
    发明授权
    Recessed channel 有权
    嵌入渠道

    公开(公告)号：US06963108B1

    公开(公告)日：2005-11-08

    申请号：US10683631

    申请日：2003-10-10

    申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Emmanuil H. Lingunis

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/04 ,  H01L29/78 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/045 ,  H01L29/66621 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/792

    摘要： A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.

    摘要翻译： 描述了具有减小的短通道效应的存储单元。 在半导体衬底中形成沟槽区。 源极区域和漏极区域形成在沟槽区域的相对侧上，其中源极区域的底部和漏极区域的底部在沟槽区域的地板的上方。 在源极区域和漏极区域之间的半导体衬底的沟槽区域中形成栅极电介质层。 在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。 控制栅极形成在凹陷沟道区域上方的半导体衬底上，其中控制栅极通过栅极介电层与凹陷沟道区分离。

    Memory array having shallow bit line with silicide contact portion and method of formation
    5.
    发明授权
    Memory array having shallow bit line with silicide contact portion and method of formation 有权
    具有硅化物接触部分的浅位线的存储器阵列和形成方法

    公开(公告)号：US06744105B1

    公开(公告)日：2004-06-01

    申请号：US10382731

    申请日：2003-03-05

    申请人： Cinti Xiaohua Chen ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Weidong Qian ,  Jean Yee-Mei Yang

    发明人： Cinti Xiaohua Chen ,  Hiroyuki Kinoshita ,  Jeff P. Erhardt ,  Weidong Qian ,  Jean Yee-Mei Yang

    IPC分类号： H01L2976

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    摘要： A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.

    摘要翻译： 一种具有多个电荷俘获介质存储器件的核心存储器阵列。 核心存储器阵列可以包括具有形成在其中的第一半导体位线和第二半导体位线的衬底和插入在第一和第二位线之间的体区。 可以在身体区域上形成设置有介电电荷俘获层和第二介电层的第一介电层。 至少一条字线可以设置在第二电介质层上，该第二电介质层限定了身体区域内的通道。 每个位线可以包括具有位线的局部金属化部分的位线接触组件和穿过电介质区域的导电通孔。

    Partially de-coupled core and periphery gate module process
    8.
    发明授权
    Partially de-coupled core and periphery gate module process 有权
    部分解耦核心和周边门模块工艺

    公开(公告)号：US06835662B1

    公开(公告)日：2004-12-28

    申请号：US10619797

    申请日：2003-07-14

    申请人： Jeff P. Erhardt ,  Hiroyuki Kinoshita ,  Cyrus Tabery

    发明人： Jeff P. Erhardt ,  Hiroyuki Kinoshita ,  Cyrus Tabery

    IPC分类号： H01L21302

    CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/115

    摘要： The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.

    摘要翻译： 本发明是一种制造结构的装置和方法。 该方法包括图案化层以包括线和空间图案的步骤。 在第一区域中的线和空间图案的空间包括在光刻的分辨率极限下小于可实现的第一临界尺寸。 第二区域中的线和空间图案的线包括在光刻的分辨率极限下可实现的第二临界尺寸。 在用于形成结构的掩模层的一条线上形成侧壁间隔物。 该方法使用一个关键的屏蔽步骤和两个非关键的屏蔽步骤。

    Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing
    9.
    发明授权
    Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing 有权
    保护电荷捕获电介质闪存器件免受BEOL处理中的紫外线引起的充电

    公开(公告)号：US07118967B1

    公开(公告)日：2006-10-10

    申请号：US10368696

    申请日：2003-02-19

    申请人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

    发明人： Minh V. Ngo ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Cyrus Tabery ,  John Caffall ,  Tyagamohan Gottipati ,  Dawn Hopper

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7923 ,  H01L29/66833 ,  Y10S438/954

    摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

    摘要翻译： 一种保护电荷捕获电介质闪存单元免受UV感应充电的方法，包括在半导体器件中制造包括电荷捕获介电电荷存储层的电荷捕获电介质闪存单元; 并且在形成电荷捕获介电电荷存储层之后的处理步骤期间，保护电荷捕获电介质闪速存储器单元暴露于足以在电荷俘获电介质闪存单元中沉积不可擦除电荷的UV辐射水平。 在一个实施例中，保护步骤是通过选择不包括半导体器件的使用，产生或曝光到足以沉积不可擦除电荷的紫外线辐射的水平的BEOL制造中的工艺进行的。