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    Dynamic semiconductor memory device and method for initializing a dynamic semiconductor memory device
    1.
    发明授权
    Dynamic semiconductor memory device and method for initializing a dynamic semiconductor memory device 有权
    用于初始化动态半导体存储器件的动态半导体存储器件和方法

    公开(公告)号：US06175531B1

    公开(公告)日：2001-01-16

    申请号：US09343429

    申请日：1999-06-30

    申请人： Martin Buck ,  Helmut Fischer ,  Heinrich Hemmert ,  Bret Johnson ,  Sebastian Kuhne

    发明人： Martin Buck ,  Helmut Fischer ,  Heinrich Hemmert ,  Bret Johnson ,  Sebastian Kuhne

    IPC分类号： G11C700

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： A dynamic semiconductor memory device of the random access type having an initialization circuit which controls the switch-on operation of the semiconductor memory device and of its circuit components. The initialization circuit supplies a supply voltage stable signal once the supply voltage has been stabilized after the switching-on of the semiconductor memory device. The initialization circuit has an advance detector circuit, which detects a predetermined level state of an externally applied clock control signal chronologically before the supply voltage stable signal is generated and, as a reaction to this, supplies a first enable signal for unlatching the control circuit provided for the proper operation of the semiconductor memory device.

    摘要翻译： 一种具有控制半导体存储器件及其电路部件的接通操作的初始化电路的随机存取型动态半导体存储器件。 一旦电源电压在半导体存储器件接通之后稳定，初始化电路就提供电源电压稳定信号。 初始化电路具有提前检测电路，其在产生电源电压稳定信号之前按时间顺序检测外部施加的时钟控制信号的预定电平状态，并且作为其反应，提供用于解锁所提供的控制电路的第一使能信号 用于半导体存储器件的正常操作。

    Integrated circuit with a differential amplifier
    4.
    发明授权
    Integrated circuit with a differential amplifier 有权
    集成电路与差分放大器

    公开(公告)号：US06477099B2

    公开(公告)日：2002-11-05

    申请号：US09761815

    申请日：2001-01-16

    申请人： Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

    发明人： Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

    IPC分类号： G11C702

    CPC分类号： H03F3/45183

    摘要： An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

    摘要翻译： 集成电路在具有两个输入晶体管，负载元件和电源的基本电路中具有差分放大器。 电源具有N型沟道MOS晶体管，其受控路径连接到输入晶体管和电源的供电端子。 晶体管的控制端子连接到相对于参考电位为正的电位。 电源的供电端子连接到相对于参考电位为负的电位，并且由用于关断DRAM存储器的单元场晶体管的电压源可用。 以这种方式增加的栅极 - 源极电压改善了电路相对于电位波动的行为，并且允许晶体管的更有利的尺寸。

    Test of a semiconductor memory having a plurality of memory banks
    6.
    发明授权
    Test of a semiconductor memory having a plurality of memory banks 失效
    具有多个存储体的半导体存储器的测试

    公开(公告)号：US06754116B2

    公开(公告)日：2004-06-22

    申请号：US10198575

    申请日：2002-07-18

    申请人： Thomas Janik ,  Sebastian Kuhne

    发明人： Thomas Janik ,  Sebastian Kuhne

    IPC分类号： G11C700

    CPC分类号： G11C29/26

    摘要： A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands, each for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.

    摘要翻译： 可以通过同时询问存储器组的命令来产生和测试自检的方法和半导体电路包括用于执行内置自检和生成命令的处理器，每个用于仅测试相应的单个存储器 银行和连接在下游的附加处理器形成更复杂的多银行命令。 这种多单元命令形成能够进行更多样化的存储器测试并且更快地进行。 主要地，使用传统的单行命令的组合的这种多存储体命令生成的优点是不会从头开始重新开发传统的BIST处理器。 仅需要将逻辑电路连接到组合的常规命令的下游逻辑电路以形成多存储体命令。 结果，可以通过非常低的开发费用来生成同时访问多个存储体的复杂的自检命令。

    Pulse generator for generating an output in response to a delay time
    8.
    发明授权
    Pulse generator for generating an output in response to a delay time 有权
    脉冲发生器，用于响应延迟时间产生输出

    公开(公告)号：US06476657B2

    公开(公告)日：2002-11-05

    申请号：US09758998

    申请日：2001-01-11

    申请人： Sebastian Kuhne

    发明人： Sebastian Kuhne

    IPC分类号： G06F104

    CPC分类号： H03K5/06 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00293

    摘要： A pulse generator circuit, in particular for use in or for integrated circuits, which, in the usual way, has a number of inverting elements connected in series, a logic combining element and a delay element. A buffer circuit provided in accordance with the invention ensures that a minimum pulse length of the output pulse generated in response to the input signal is ensured even in the case of an input signal of a very short duration.

    摘要翻译： 脉冲发生器电路，特别是用于或用于集成电路，其以通常的方式具有串联连接的多个反相元件，逻辑组合元件和延迟元件。 根据本发明提供的缓冲电路确保即使在非常短的持续时间的输入信号的情况下也能确保响应于输入信号产生的输出脉冲的最小脉冲长度。

    Integrated semiconductor memory with control device for clock-synchronous writing and reading
    10.
    发明授权
    Integrated semiconductor memory with control device for clock-synchronous writing and reading 有权
    集成半导体存储器，具有时钟同步写入和读取的控制器件

    公开(公告)号：US06188638B1

    公开(公告)日：2001-02-13

    申请号：US09384701

    申请日：1999-08-27

    申请人： Sebastian Kuhne

    发明人： Sebastian Kuhne

    IPC分类号： G11C818

    CPC分类号： G11C7/1045 ,  G11C7/1072

    摘要： In an integrated semiconductor memory with clock-synchronous read and write accesses, the access control device is configured to be switchable between one-way and two-way data strobe mode. The access mode is set using a bond option or a mode register.

    摘要翻译： 在具有时钟同步读写访问的集成半导体存储器中，访问控制装置被配置为可在单向和双向数据选通模式之间切换。 访问模式使用键选项或模式寄存器设置。