公开(公告)号：US20170125591A1

公开(公告)日：2017-05-04

申请号：US15408294

申请日：2017-01-17

申请人： Martin D. GILES ,  Annalisa CAPPELLANI ,  Sanaz KABEHIE ,  Rafael RIOS ,  Cory E. WEBER ,  Aaron A. BUDREVICH

发明人： Martin D. GILES ,  Annalisa CAPPELLANI ,  Sanaz KABEHIE ,  Rafael RIOS ,  Cory E. WEBER ,  Aaron A. BUDREVICH

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28593 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3065 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

公开(公告)号：US20170141239A1

公开(公告)日：2017-05-18

申请号：US15405899

申请日：2017-01-13

申请人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

发明人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20150325648A1

公开(公告)日：2015-11-12

申请号：US14803919

申请日：2015-07-20

申请人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

发明人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/268

CPC分类号： H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

摘要翻译： 描述了具有非离散源极和漏极区域的纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。 每个纳米线包括设置在纳米线中的离散通道区域。 栅电极堆叠围绕多个垂直堆叠的纳米线。 一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

公开(公告)号：US20140326952A1

公开(公告)日：2014-11-06

申请号：US14274592

申请日：2014-05-09

申请人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

发明人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US20170133277A1

公开(公告)日：2017-05-11

申请号：US15411095

申请日：2017-01-20

申请人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

发明人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L27/092 ,  H01L21/84

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.