公开(公告)号：US20170125591A1

公开(公告)日：2017-05-04

申请号：US15408294

申请日：2017-01-17

申请人： Martin D. GILES ,  Annalisa CAPPELLANI ,  Sanaz KABEHIE ,  Rafael RIOS ,  Cory E. WEBER ,  Aaron A. BUDREVICH

发明人： Martin D. GILES ,  Annalisa CAPPELLANI ,  Sanaz KABEHIE ,  Rafael RIOS ,  Cory E. WEBER ,  Aaron A. BUDREVICH

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28593 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3065 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

公开(公告)号：US20140167108A1

公开(公告)日：2014-06-19

申请号：US13717282

申请日：2012-12-17

申请人： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

发明人： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

摘要翻译： 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US20080157058A1

公开(公告)日：2008-07-03

申请号：US11647989

申请日：2006-12-29

申请人： Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. K. Liu

发明人： Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. K. Liu

IPC分类号： H01L29/06 ,  H01L21/04

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02549 ,  H01L21/02584 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7784

摘要： A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm−2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

摘要翻译： 描述了器件级III-V量子阱结构及其制造方法。 本发明的实施方案能够形成缺陷密度低于1×10 8 cm -3的III-V InSb量子阱器件层。 在本发明的一个实施例中，Δ掺杂层设置在掺杂剂偏析屏障上，以便将δ掺杂剂限制在δ掺杂层内并抑制δ掺杂剂表面偏析。

公开(公告)号：US20140291772A1

公开(公告)日：2014-10-02

申请号：US14301281

申请日：2014-06-10

申请人： Willy RACHMADY ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

发明人： Willy RACHMADY ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC分类号： H01L29/06 ,  H01L21/306 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

摘要翻译： 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US08394694B2

公开(公告)日：2013-03-12

申请号：US11725521

申请日：2007-03-19

申请人： Adrien R. Lavoie ,  Aaron A. Budrevich ,  Ashutosh Ashutosh ,  Huicheng Chang

发明人： Adrien R. Lavoie ,  Aaron A. Budrevich ,  Ashutosh Ashutosh ,  Huicheng Chang

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/3003 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/66545 ,  H01L29/66772

摘要： A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.

摘要翻译： 一种用于提高高k栅极电介质层的可靠性的方法包括将贵金属掺入到包含高k栅极电介质层并在分子氢或含氘气氛中退火晶体管栅极叠层的晶体管栅极堆叠中。 退火过程将至少一部分分子氢或氘驱向高k栅介质层。 当分子氢或氘与贵金属接触时，它被转化为能够处理高k栅介质层并提高其可靠性的原子氢或氘。

公开(公告)号：US08222746B2

公开(公告)日：2012-07-17

申请号：US11540386

申请日：2006-09-28

申请人： Adrien R. Lavoie ,  Juan E. Dominguez ,  Aaron A. Budrevich

发明人： Adrien R. Lavoie ,  Juan E. Dominguez ,  Aaron A. Budrevich

IPC分类号： H01L23/48

CPC分类号： C23C28/00 ,  C23C28/021 ,  C23C28/023 ,  C23C28/028 ,  C23C28/321 ,  C23C28/322 ,  C23C28/325 ,  C23C28/34 ,  C23C28/345

摘要： Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk metal and the dielectric layer. The barrier layer may include one or more metals selected from iridium, platinum, palladium, rhodium, osmium, gold, silver, rhenium, ruthenium, tungsten, and nickel.

摘要翻译： 公开了贵金属阻挡层。 在一个方面，一种装置可以包括衬底，在衬底上的电介质层，以及电介质层内的互连结构。 互连结构可以具有体金属和阻挡层。 阻挡层可以设置在本体金属和电介质层之间。 阻挡层可以包括选自铱，铂，钯，铑，锇，金，银，铼，钌，钨和镍中的一种或多种金属。

公开(公告)号：US20100252929A1

公开(公告)日：2010-10-07

申请号：US12818948

申请日：2010-06-18

申请人： Aaron A. Budrevich ,  Adrien R. Lavoie

发明人： Aaron A. Budrevich ,  Adrien R. Lavoie

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76871 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

摘要翻译： 描述了包含用于保护金属互连的II族元素合金的多个金属互连以及形成并结合第II族元素合金的方法。 在一个实施例中，使用II族元素合金作为种子层或其一部分，其降低线电阻并增加金属互连的机械强度。 在另一个实施方案中，使用II族元素合金形成阻挡层，除了降低线电阻和增加机械完整性之外，还增加了金属互连的化学完整性。

公开(公告)号：US07759241B2

公开(公告)日：2010-07-20

申请号：US11521941

申请日：2006-09-15

申请人： Aaron A. Budrevich ,  Adrien R. Lavoie

发明人： Aaron A. Budrevich ,  Adrien R. Lavoie

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76871 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

摘要翻译： 描述了包含用于保护金属互连的II族元素合金的多个金属互连和形成并结合第II族元素合金的方法。 在一个实施例中，使用II族元素合金作为种子层或其一部分，其降低线电阻并增加金属互连的机械强度。 在另一个实施方案中，使用II族元素合金形成阻挡层，除了降低线电阻和增加机械完整性之外，还增加了金属互连的化学完整性。

公开(公告)号：US20140035059A1

公开(公告)日：2014-02-06

申请号：US13995419

申请日：2011-12-19

申请人： Martin D. Giles ,  Annalisa Cappellani ,  Sanaz Kabehie ,  Rafael Rios ,  Cory E. Weber ,  Aaron A. Budrevich

发明人： Martin D. Giles ,  Annalisa Cappellani ,  Sanaz Kabehie ,  Rafael Rios ,  Cory E. Weber ,  Aaron A. Budrevich

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L29/7848 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28593 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3065 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

摘要翻译： 描述具有金属源极和漏极区域的半导体器件。 例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。 金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。 金属源极和漏极区域中的每个具有轮廓。 第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。 第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

公开(公告)号：US07842983B2

公开(公告)日：2010-11-30

申请号：US12215250

申请日：2008-06-26

申请人： Ashutosh Ashutosh ,  Huicheng Chang ,  Adrien R. Lavoie ,  Aaron A. Budrevich

发明人： Ashutosh Ashutosh ,  Huicheng Chang ,  Adrien R. Lavoie ,  Aaron A. Budrevich

IPC分类号： H01L29/76

CPC分类号： H01L21/3003 ,  H01L21/26506 ,  H01L29/665

摘要： A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.

摘要翻译： 器件在氘气氛中退火。 氘渗透到边界，被氘钝化。