公开(公告)号：US09029959B2

公开(公告)日：2015-05-12

申请号：US13537101

申请日：2012-06-29

申请人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

发明人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, Jr. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

IPC分类号： H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L21/02321 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517

摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

公开(公告)号：US20140001570A1

公开(公告)日：2014-01-02

申请号：US13537101

申请日：2012-06-29

申请人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

发明人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

IPC分类号： H01L27/088 ,  H01L21/31

CPC分类号： H01L21/02321 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517

摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

公开(公告)号：US20130105894A1

公开(公告)日：2013-05-02

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L27/12 ,  H01L21/04

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US20130105896A1

公开(公告)日：2013-05-02

申请号：US13625350

申请日：2012-09-24

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L27/12

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US09040399B2

公开(公告)日：2015-05-26

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L21/425 ,  H01L29/66

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US09029172B2

公开(公告)日：2015-05-12

申请号：US13354547

申请日：2012-01-20

申请人： Fen Chen ,  Roger A. Dufresne ,  Timothy D. Sullivan ,  Yanfeng Wang

发明人： Fen Chen ,  Roger A. Dufresne ,  Timothy D. Sullivan ,  Yanfeng Wang

IPC分类号： H01L21/00 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L2924/00 ,  H01L2924/0002

摘要： An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.

摘要翻译： 提供片上多点接触式过程监测和可靠性评估系统及其使用方法。 一种方法包括确定与相应的一个或多个原始半导体结构相对应的一个或多个浅沟槽隔离（STI）测量结构中的每一个的击穿电场。 该方法还包括确定与相应的一个或多个原始半导体结构相对应的一个或多个衬底测量结构中的每一个的击穿电压。 该方法还包括基于所确定的击穿电场和所确定的击穿电压，确定一个或多个原始半导体结构中的每一个的栅极和触点之间的空间。

公开(公告)号：US08797112B2

公开(公告)日：2014-08-05

申请号：US13400129

申请日：2012-02-20

申请人： Peng Han ,  Dawei Guo Guo ,  Jiazhou Liu ,  Yanfeng Wang

发明人： Peng Han ,  Dawei Guo Guo ,  Jiazhou Liu ,  Yanfeng Wang

IPC分类号： H03C1/00

CPC分类号： H03C1/36 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0033 ,  H03D2200/0052 ,  H04L27/04

摘要： An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal.

摘要翻译： ASK调制器包括：基带单元，其获得包括至少一个幅度值的序列，并且对所述至少一个幅度值中的每一个增加附加值以生成修改的序列; 耦合到所述基带单元的数模转换器，所述数模转换器转换所述经修改的序列以产生第一信号，所述附加值基于所述数模转换器的半标度来确定; 以及混合器，其接收第一信号和第二信号，并通过将第一信号与第二信号混合来产生调制信号。

公开(公告)号：US08729637B2

公开(公告)日：2014-05-20

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/70 ,  H01L21/20 ,  H01L21/00

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。

公开(公告)号：US08697702B2

公开(公告)日：2014-04-15

申请号：US13129903

申请日：2009-11-30

申请人： Yanfeng Wang ,  Thea Kalebic ,  Timothy P Hughes ,  Deborah White

发明人： Yanfeng Wang ,  Thea Kalebic ,  Timothy P Hughes ,  Deborah White

IPC分类号： A61K31/497

CPC分类号： A61K31/506

摘要： The present invention relates to a method of treating Philadelphia-positive leukemia (Ph+ leukemia), in a particular chronic myeloid leukemia (CML), in a human patient population. More specifically, the present invention pertains to a method of treating Ph+ leukemia, such as CML or Phi+ ALL, in a human patient suffering from Ph+ leukemia comprising the steps of (a) administering a predetermined fixed amount of Imatinib as a free base or in the form of a pharmaceutically acceptable salt thereof to the human patient, (b) collecting at least one blood sample from the patient, e.g. within the first 12 months of treatment, (c) determining the plasma trough level (Cmin) of Imatinib, (d) determining the OCT-1 Activity in the blood sample, and (e) adjusting the dose of Imatinib applied to the individual patient in a manner that an Imatinib Cmin value is achieved in the patient of at least 800 ng/mL, if in step (c) an Imatinib Cmin value of less than 800 ng/mL is found and in step (d) an OCT-1 Activity is found below 6.0 to 10.0 ng/200,000 cells.

摘要翻译： 本发明涉及在人类患者群体中治疗特定慢性骨髓性白血病（CML）中的费城阳性白血病（Ph +白血病）的方法。 更具体地，本发明涉及在患有Ph +白血病的人类患者中治疗Ph +白血病（例如CML或Phi + ALL）的方法，包括以下步骤：（a）施用预定的固定量的伊马替尼作为游离碱或 其药学上可接受的盐的形式提供给人类患者，（b）从患者收集至少一种血液样品， 在治疗的头12个月内，（c）确定伊马替尼的血浆谷值（Cmin），（d）确定血液样品中的OCT-1活性，和（e）调整施用于个体患者的伊马替尼剂量 如果在步骤（c）中发现伊马替尼Cmin值小于800ng / mL，并且在步骤（d）中OCT-1 活性发现低于6.0至10.0ng / 20万个细胞。

公开(公告)号：US07943467B2

公开(公告)日：2011-05-17

申请号：US12016317

申请日：2008-01-18

申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。