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公开(公告)号：US5023682A
公开(公告)日：1991-06-11
申请号：US370662
申请日：1989-06-23
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/00 , H01L27/108
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), thin p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness. Films 16 and 17 are added to prevent an increase in diffusion resistance of the regions (6, 7) and the interconnection resistance of the second gate electrode (3). An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner.A bit line is formed on the semiconductor region and connected thereto. An interlayer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n.sup.+ -type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorous oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
摘要翻译： 半导体存储器件包括p型半导体衬底（1），形成在其上的薄p +型区域（15,80），被p +型区域（15,80）包围的n +型区域（6,7） ，形成在n +型区域（6）的电荷存储区域上的第一栅电极（2）和形成在p +型区域（80）上并用作字线的第二栅电极（3）。 p +型区域（15,80）防止电子从α射线诱发的电子 - 空穴对中流出，以防止软错误的发生。 有利地，用于控制装置的传输门的阈值电压的薄p +层被扩展，并且还用于防止这种软错误，从而为装置提供减少的体积。 为了进一步减小体积，n +型区域（6,7）的厚度也减小。 加入薄膜16和17以防止区域（6,7）的扩散阻力的增加和第二栅电极（3）的互连电阻的增加。 在第二栅电极（3）的侧壁上形成氧化膜（16），在n +型区域（6,7）上形成硅化钛膜（17），硅化钛膜（18）为 以自对准的方式形成在第二栅电极（3）上。 在半导体区域上形成位线并与其连接。 可选地，在位线和位于半导体n +型区域上的难熔金属硅化物膜之间形成层间绝缘膜。 层间绝缘膜优选包含氧化硅膜或氧化磷膜。 最后，可选地在位线上形成保护膜。 保护膜优选由具有低介电常数的材料制成。
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公开(公告)号：US4702797A
公开(公告)日：1987-10-27
申请号：US943053
申请日：1986-12-18
IPC分类号： H01L27/10 , G11C11/34 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/08 , H01L29/10 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L27/1085 , H01L27/10805 , H01L29/0847 , H01L29/1083 , Y10S438/953
摘要： A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.+ -type regions (80a, 81a), so that operation of a parasitic pnp transistor is not caused.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在p型半导体衬底（1）上形成存储单元部分（2,4,6,11），形成栅极绝缘膜（5）和栅电极（3） ）各自具有比原始宽度大约1μm的离子注入p型杂质，利用栅极绝缘膜（5）和栅电极（3）作为掩模，形成p +型区域（ 将栅极绝缘体膜（5）和栅电极（3）的侧壁蚀刻到原始宽度，然后将这些区域的n型杂质离子注入作为掩模，形成n +型 区域（80,81），并对这些区域（80,81,120,121）进行热处理，以形成区域（80a，81a，120a，121a）。 p +型区域（120a，121a）防止电子从由α射线诱发的电子 - 空穴对中流出，以防止发生软错误。 p +型区域（120a，121a）位于n +型区域（80a，81a）内部，从而不产生寄生pnp晶体管的操作。
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3.发明授权Structure for isolating semiconductor components on an integrated circuit and a method of manufacturing therefor 失效用于隔离集成电路上的半导体部件的结构及其制造方法
公开(公告)号：US4942448A
公开(公告)日：1990-07-17
申请号：US262303
申请日：1988-10-25
IPC分类号： H01L21/76 , H01L21/763 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/76 , H01L21/763
摘要： A semiconductor apparatus having a region for isolation between devices comprises a semiconductor substrate, a polycrystalline silicon layer portions selectively formed to be spaced apart from each other on the semiconductor substrate, an impurity diffused region formed under the polycrystalline silicon layer, and a silicon oxide film for filling in a space between the respective adjacent portions of the polycrystalline silicon layer. The impurity diffused region constitutes a source or drain region of a field effect device such as a MOS transistor isolated by the silicon oxide film.
摘要翻译： 具有用于在器件之间隔离的区域的半导体器件包括半导体衬底，选择性地形成为在半导体衬底上彼此间隔开的多晶硅层部分，形成在多晶硅层下面的杂质扩散区域和氧化硅膜 用于填充多晶硅层的各个相邻部分之间的空间。 杂质扩散区域构成诸如通过氧化硅膜隔离的MOS晶体管的场效应器件的源极或漏极区域。
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4.发明授权Manufacturing method for semiconductor memory device having stacked trench capacitors and improved intercell isolation 失效具有层叠沟槽电容器和改进的晶胞间隔离的半导体存储器件的制造方法
公开(公告)号：US5258321A
公开(公告)日：1993-11-02
申请号：US896872
申请日：1992-06-10
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor memory device having memory cells formed adjacent to each other comprises a P type semiconductor substrate having adjacent two trenches, a P.sup.+ impurity region formed in the side portions and the bottom portions of the trenches, n type first polysilicon layers serving as common electrodes formed in the upper portion of the P.sup.+ impurity region through an insulating film, second polysilicon layers formed inside and in the upper portion of the trenches formed of the first polysilicon layers through an insulating film, and a third polysilicon layer formed on the second polysilicon layers, only the third polysilicon layer constituting a connecting electrode between the adjacent memory cells.
摘要翻译： 具有彼此相邻形成的存储单元的半导体存储器件包括具有相邻的两个沟槽的P型半导体衬底，形成在沟槽的侧部和底部中的P +杂质区，形成用作共同电极的n型第一多晶硅层 通过绝缘膜在P +杂质区的上部，通过绝缘膜形成在由第一多晶硅层形成的沟槽的内部和上部的第二多晶硅层，以及形成在第二多晶硅层上的第三多晶硅层， 只有第三多晶硅层构成相邻存储单元之间的连接电极。
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公开(公告)号：US5268321A
公开(公告)日：1993-12-07
申请号：US295101
申请日：1989-01-09
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10805
摘要： A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. Therefore, increase of interconnection resistance of the second gate electrode (3 ) and diffusion resistance of the n.sup.+ -type regions (6, 7) is prevented. A bit line is formed on the semiconductor region and connected thereto. An inner layer insulation film is optionally connected thereto. An inner layer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n.sup.+ -type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorus oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
摘要翻译： 半导体存储器件包括p型半导体衬底（1），形成在其上的p +型区域（15,80），被p +型区域（15,80）包围的n +型区域（6,7） 形成在n +型区域（6）中的电荷存储区域上的第一栅电极（2）和形成在p +型区域（80）上并用作字线的第二栅电极（3）。 p +型区域（15,80）防止电子从α射线诱发的电子 - 空穴对中流出，以防止软错误的发生。 在第二栅电极（3）的侧壁上形成氧化膜（16），在n +型区域（6,7）上形成硅化钛膜（17），硅化钛膜（18）为 以自对准的方式形成在第二栅电极（3）上。 因此，防止了第二栅电极（3）的互连电阻的增加和n +型区域（6,7）的扩散电阻。 在半导体区域上形成位线并与其连接。 内层绝缘膜可选地连接到其上。 可选地，在位线和位于半导体n +型区域上的难熔金属硅化物膜之间形成内层绝缘膜。 层间绝缘膜优选包含氧化硅膜或氧化磷膜。 最后，可选地在位线上形成保护膜。 保护膜优选由具有低介电常数的材料制成。
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6.发明授权Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step 失效使用斜离子注入步骤制造MOS型场效应晶体管的方法
公开(公告)号：US5258319A
公开(公告)日：1993-11-02
申请号：US747589
申请日：1991-08-20
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/66659 , H01L29/7836
摘要： An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.
摘要翻译： 本发明的MOSFET（金属氧化物半导体场效应晶体管）包括在半导体衬底中彼此间隔开形成的两个源极掺杂杂质区。 两个杂质区域的至少漏极侧具有所谓的LDD结构，其中较高浓度的区域和较低浓度的区域被设定。 在源极和漏极之间的半导体衬底上形成具有矩形横截面的栅电极，其间插入绝缘膜。 栅电极完全覆盖LDD结构的较低浓度区域。 栅极侧面的位置与较高浓度区域的端面大致对准。 LDD浓度较低的杂质区通过斜离子注入形成。
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公开(公告)号：US5061975A
公开(公告)日：1991-10-29
申请号：US658430
申请日：1991-02-20
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/66659 , H01L29/7836
摘要： An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.
摘要翻译： 本发明的MOSFET（金属氧化物半导体场效应晶体管）包括在半导体衬底中彼此间隔开形成的两个源极掺杂杂质区。 两个杂质区域的至少漏极侧具有所谓的LDD结构，其中较高浓度的区域和较低浓度的区域被设定。 在源极和漏极之间的半导体衬底上形成具有矩形横截面的栅电极，其间插入绝缘膜。 栅电极完全覆盖LDD结构的较低浓度区域。 栅极侧面的位置与较高浓度区域的端面大致对准。 LDD浓度较低的杂质区通过斜离子注入形成。
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8.发明授权Semiconductor device having a retrograde well structure and method of manufacturing thereof 失效具有逆行井结构的半导体装置及其制造方法公开(公告)号：US06420763B1
公开(公告)日：2002-07-16
申请号：US08917528
申请日：1997-08-26
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L27/1052
摘要： A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.
摘要翻译： 半导体衬底是第一导电类型并且具有逆向阱杂质浓度。 在半导体衬底的主表面上形成第一导电类型并具有杂质浓度峰值的第二杂质浓度的第一种。 第三杂质浓度的第一杂质层与逆行井的下侧接触。 第三杂质浓度小于第一杂质浓度和第二杂质浓度的杂质浓度峰值。 在逆行井上形成一个元件。
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9.发明授权Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof 失效包含氧化硅膜和氮化氧化膜作为栅极绝缘膜的场效应晶体管及其制造方法
公开(公告)号：US5369297A
公开(公告)日：1994-11-29
申请号：US930932
申请日：1992-08-18
申请人： Shigeru Kusunoki , Masahide Inuishi
发明人： Shigeru Kusunoki , Masahide Inuishi
IPC分类号： H01L21/266 , H01L21/28 , H01L21/314 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28185 , H01L21/266 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7836 , H01L29/78621 , Y10S257/90
摘要： An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.
摘要翻译： 一种N型场效应晶体管，其具有对热载流子的较高的电阻率，并且即使在低栅极电压下使用时也具有更高的电流处理能力，并且提供了制造这种晶体管的方法。 在排水雪崩热载体注入区域上形成氮化氧化物膜。 与氧化硅膜相比，氮化氧化物膜对排水雪崩热载流子具有高度阻力。 氧化硅膜形成在通道热电子注入区域上。 与氮化氧化物膜相比，氧化硅膜对沟道热电子具有高度的阻力。 栅绝缘膜的主要部分是氧化硅膜。 与氮化氧化物膜相比，氧化硅膜在低栅极电压下表现出更高的电流处理能力。
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公开(公告)号：US5089865A
公开(公告)日：1992-02-18
申请号：US462536
申请日：1990-01-03
IPC分类号： H01L21/336 , H01L29/78 , H01L29/10 , H01L29/04
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.
摘要翻译： 在具有LDD和自对准硅化物结构的MIS晶体管中，高和低杂质浓度源极/漏极区域之间的边界位置和源极/漏极区域上的自对准硅化物层的位置在制造期间被独立地控制，使用双 门侧壁结构。 因此，改善的MIS晶体管相对于双栅极侧壁结构的界面在其与控制栅电极之间或之后的高杂质浓度源极/漏极区域之间具有边界。
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