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97 条记录 (耗时 0.031 秒)

    PREDICTIVE SEQUENTIAL CALCULATION DEVICE
    3.
    发明申请
    PREDICTIVE SEQUENTIAL CALCULATION DEVICE 有权
    预测顺序计算装置

    公开(公告)号：US20140189416A1

    公开(公告)日：2014-07-03

    申请号：US14237312

    申请日：2011-08-26

    申请人： Yoshiyuki Tajima ,  Koichiro Iijima ,  Tohru Watanabe ,  Takaharu Ishida

    发明人： Yoshiyuki Tajima ,  Koichiro Iijima ,  Tohru Watanabe ,  Takaharu Ishida

    IPC分类号： G06F1/10

    CPC分类号： G06F9/4881 ,  G06F9/4887 ,  G06F9/5027 ,  G06F11/30 ,  G06F11/34 ,  H02J3/14 ,  H02J4/00 ,  H02J13/0079 ,  H02J2003/007 ,  H02J2003/143 ,  Y02B70/3225 ,  Y02B70/3266 ,  Y04S20/222 ,  Y04S20/242

    摘要： A calculation device is provided that executes calculations within real-time restrictions. The calculation device implements a step of predicting a processing time of a calculation related to the amount and property of input data based on a prediction model; a step of adjusting the processing time by decreasing the amount of data used for the calculation or decreasing the number of iterative calculations when the processing time exceeds a time slice allocated to the calculation; a step of executes the calculation using the adjusted processing time; a step of updating, as required, the prediction model used for predicting the processing time according to the result of the calculation which is executed in a period where the calculation is not performed while implementing a change of the amount of data or the number of iterative calculations or change to an approximation.

    摘要翻译： 提供了一种在实时限制内执行计算的计算设备。 计算装置实现基于预测模型来预测与输入数据的量和属性相关的计算的处理时间的步骤; 当处理时间超过分配给计算的时间片时，通过减少用于计算的数据量或减少迭代次数来调整处理时间的步骤; 使用调整后的处理时间执行计算的步骤; 根据需要更新根据在不执行计算期间执行的计算结果来预测处理时间的预测模型的步骤，同时实现数据量的改变或迭代次数 计算或更改为近似值。

    Image signal processor and deficient pixel detection method
    5.
    发明授权
    Image signal processor and deficient pixel detection method 有权
    图像信号处理器和缺陷像素检测方法

    公开(公告)号：US07755680B2

    公开(公告)日：2010-07-13

    申请号：US11426754

    申请日：2006-06-27

    申请人： Tohru Watanabe

    发明人： Tohru Watanabe

    IPC分类号： H04N9/64

    CPC分类号： G09G3/006 ,  G06T5/005 ,  G06T5/20 ,  G06T7/0002 ,  G09G2330/10 ,  H01L27/14806 ,  H04N5/21 ,  H04N5/367 ,  H04N5/3675

    摘要： A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.

    摘要翻译： 不足候选检测电路通过将目标像素的图像信号与周边像素的图像信号进行比较来检测缺陷像素候选，并且将不良像素候选的地址信息存储在位置存储电路中。 缺陷判定电路基于存储在位置存储电路中的地址信息重复不良像素的判定次数，根据判定结果的连续性来判定缺陷像素的地址信息。 缺陷登记电路将确定的地址信息登记在位置存储电路中。 缺陷校正电路根据缺陷像素的注册地址信息校正缺陷像素的图像信号。

    IMAGE SIGNAL PROCESSOR FOR USE WITH A SOLID-STATE IMAGING DEVICE
    6.
    发明申请
    IMAGE SIGNAL PROCESSOR FOR USE WITH A SOLID-STATE IMAGING DEVICE 有权
    用于固态成像装置的图像信号处理器

    公开(公告)号：US20080170153A1

    公开(公告)日：2008-07-17

    申请号：US12041740

    申请日：2008-03-04

    申请人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

    发明人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

    IPC分类号： H04N5/225 ,  H04N3/14

    CPC分类号： H04N5/23241 ,  H04N5/335

    摘要： A signal processor for reducing power consumption. The signal processor includes a signal processing circuit and a first regulator connected to the signal processing circuit. The first regulator receives an external regulated voltage from an external regulator connected to the signal processor and generates an internal regulated voltage that is in accordance with an output level of a CCD image sensor. The signal processing circuit operates with the internal regulated voltage and performs a predetermined signal processing on an image signal generated by the CCD image sensor.

    摘要翻译： 用于降低功耗的信号处理器。 信号处理器包括信号处理电路和连接到信号处理电路的第一调节器。 第一调节器从连接到信号处理器的外部调节器接收外部调节电压，并产生与CCD图像传感器的输出电平相一致的内部调节电压。 信号处理电路以内部调节电压进行动作，对由CCD图像传感器生成的图像信号进行规定的信号处理。

    Image signal processor employing voltage regulators to decrease overall power consumption
    7.
    发明授权
    Image signal processor employing voltage regulators to decrease overall power consumption 有权
    图像信号处理器采用电压调节器来降低总体功耗

    公开(公告)号：US07110038B2

    公开(公告)日：2006-09-19

    申请号：US10208141

    申请日：2002-07-30

    申请人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

    发明人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

    IPC分类号： H04N5/225

    CPC分类号： H04N5/23241 ,  H04N5/335

    摘要： A signal processor for reducing power consumption. The signal processor includes a first regulator for generating a first regulated voltage with a power supply voltage and supplying the first regulated voltage to a signal processing circuit. A second regulator generates a second regulated voltage with the power supply voltage and supplies the second regulated voltage to an output circuit. The second regulator shifts the second regulated voltage in accordance with a change in an input level of the external device.

    摘要翻译： 用于降低功耗的信号处理器。 信号处理器包括用于产生具有电源电压的第一调节电压并将第一调节电压提供给信号处理电路的第一调节器。 第二调节器产生具有电源电压的第二调节电压，并将第二调节电压提供给输出电路。 第二调节器根据外部设备的输入电平的变化来移动第二调节电压。

    Imaging apparatus
    8.
    发明授权
    Imaging apparatus 失效

    公开(公告)号：US07027085B2

    公开(公告)日：2006-04-11

    申请号：US10235246

    申请日：2002-09-04

    申请人： Tohru Watanabe

    发明人： Tohru Watanabe

    IPC分类号： H04N5/225

    CPC分类号： H04N5/2355 ,  H04N5/235 ,  H04N5/33 ,  H04N5/335

    摘要： An imaging apparatus that has a reduced circuit scale and efficiently operates a plurality of solid-state imaging devices. The imaging apparatus includes first and second solid-state imaging devices, first and second drive circuits for driving the first and second solid-state imaging devices, and a timing control circuit for determining the vertical and horizontal scan timing of the first and second solid-state imaging devices in accordance with a reference clock signal having a fixed cycle. A selection circuit selects either one of the first and second image signals in synchronism with an operation timing of the first and second solid-state imaging devices. A signal processing circuit performs a predetermined imaging process on the selected image signal to generate image data. The selection circuit alternately selects the first and second image signals at predetermined time intervals.

    Signal processing apparatus
    9.
    发明申请
    Signal processing apparatus 有权
    信号处理装置

    公开(公告)号：US20050062862A1

    公开(公告)日：2005-03-24

    申请号：US10941531

    申请日：2004-09-15

    申请人： Hisashi Matsuyama ,  Tohru Watanabe

    发明人： Hisashi Matsuyama ,  Tohru Watanabe

    IPC分类号： H01L27/148 ,  H01L27/14 ,  H01L29/765 ,  H04N5/335 ,  H04N5/341 ,  H04N5/367 ,  H04N5/369 ,  H04N5/372 ,  H04N5/378 ,  H04N9/64

    CPC分类号： H04N5/3675 ,  H04N5/361

    摘要： A signal processing apparatus including a clamp pulse generation circuit for generating a clamp pulse in synchronization with an image signal, a clamp circuit for clamping a signal of a black reference value in response to the clamp pulse, and a defect detection circuit for detecting a defective pixel included in an optical black area, wherein the clamp pulse generation circuit cancels a rise of the clamp pulse when a position of the defective pixel detected by the defect detecting circuit and a position of a rise state of the clamp pulse overlap with each other.

    摘要翻译： 一种信号处理装置，包括用于产生与图像信号同步的钳位脉冲的钳位脉冲发生电路，用于钳位脉冲响应于黑参考值的信号的钳位电路，以及用于检测有缺陷的缺陷检测电路 包括在光学黑色区域中的像素，其中当由缺陷检测电路检测到的缺陷像素的位置和钳位脉冲的上升状态的位置彼此重叠时，钳位脉冲发生电路消除钳位脉冲的上升。