公开(公告)号：US5765625A

公开(公告)日：1998-06-16

申请号：US760339

申请日：1996-12-04

申请人： Masao Yukumoto ,  Kensuke Matsuki ,  Nobuo Shiga ,  Hitoshi Ogo

发明人： Masao Yukumoto ,  Kensuke Matsuki ,  Nobuo Shiga ,  Hitoshi Ogo

IPC分类号： B22D11/06

CPC分类号： B22D11/0611 ,  B22D11/0697

摘要： A method and apparatus for manufacturing an amorphous metal ribbon provides the following: jetting a molten metal from a nozzle, which has a slit-shaped opening, to a cooling roll, which rotates at a high speed, so as to form a puddle on the cooling roll; and spreading the puddle for rapid solidification. Additionally, the present invention provides at a position upstream from the puddle in a direction opposite the direction of rotation of the cooling roll, cleaning the surface of the cooling roll by blowing carbon dioxide gas to which ultrasonic vibration is applied.

摘要翻译： 用于制造非晶态金属带的方法和装置提供如下：从具有狭缝形开口的喷嘴将熔融金属喷射到高速旋转的冷却辊上，以在其上形成熔池 冷却辊; 并铺设水坑快速凝固。 此外，本发明提供了一种在水槽上游方向与冷却辊旋转方向相反的方向，通过吹入施加有超声波振动的二氧化碳来清洁冷却辊的表面。

公开(公告)号：US06273967B1

公开(公告)日：2001-08-14

申请号：US08791753

申请日：1997-01-29

申请人： Kensuke Matsuki ,  Fumio Kogiku ,  Nobuo Shiga ,  Masao Yukumoto

发明人： Kensuke Matsuki ,  Fumio Kogiku ,  Nobuo Shiga ,  Masao Yukumoto

IPC分类号： H01F1153

CPC分类号： C22C45/02 ,  B22D11/06

摘要： An amorphous alloy having a boron content of about 6 to 10 at %, cast into a plate, wherein the plate thickness is about 15 to 25 &mgr;m, and the surface roughness Ra0.8 of the plate is about 0.8 &mgr;m or less.

摘要翻译： 将硼含量为约6至10原子％的非晶态合金浇铸成板，其中板厚度为约15至25μm，板的表面粗糙度Ra0.8为约0.8μm或更小。

公开(公告)号：US5499673A

公开(公告)日：1996-03-19

申请号：US322955

申请日：1994-10-13

申请人： Nobuo Shiga ,  Tomohiro Marui ,  Kiyoshi Shibuya ,  Toru Sato ,  Michiharu Ozawa ,  Masao Yukumoto

发明人： Nobuo Shiga ,  Tomohiro Marui ,  Kiyoshi Shibuya ,  Toru Sato ,  Michiharu Ozawa ,  Masao Yukumoto

IPC分类号： B22D11/06

CPC分类号： B22D11/0694

摘要： A continuous thin metal strip formed by quenching on a single quenching roll is separated from the quenching roll and conveyed along a fly path to a coiling system directly or via pinch rolls. The path along which the thin metal strip flies is stabilized by a jet of a fluid jetted from a slit and biased to flow along a convex curved surface, whereby the time until the strip is taken up or nipped by the pinch rolls is shortened.

摘要翻译： 通过在单个淬火辊上淬火而形成的连续薄金属条从淬火辊分离，并且沿着飞行路径直接或通过夹送辊被输送到卷取系统。 薄金属带飞行的路径通过从狭缝喷射的流体的射流被稳定，并被偏压成沿着凸曲面流动，由此直到带被卷取辊吸收或夹持的时间被缩短。

公开(公告)号：USD396210S

公开(公告)日：1998-07-21

申请号：US55822

申请日：1996-05-03

申请人： Nobuo Shiga ,  Takeshi Sekiguchi ,  Sosaku Sawada ,  Daisuke Takagi

设计人： Nobuo Shiga ,  Takeshi Sekiguchi ,  Sosaku Sawada ,  Daisuke Takagi

公开(公告)号：US5389807A

公开(公告)日：1995-02-14

申请号：US110937

申请日：1993-08-24

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/80 ,  H01L29/812 ,  H01L33/00

CPC分类号： H01L29/8124 ,  H01L29/1029

摘要： It is an object of the present invention to provide a dual-gate type MESFET having a high drain breakdown voltage and excellent high-frequency characteristics. A semiconductor substrate used in the present invention is obtained by sequentially forming a non-doped buffer layer 2, a thin first pulse-doped layer 3 having a high impurity concentration, and a cap layer 7 on an underlying semiconductor substrate 1 by epitaxial growth. The cap layer 7 has a thin second pulse-doped layer 5 having a high impurity concentration sandwiched between non-doped layers 4 and 6. The thickness and impurity concentration of the second pulse-doped layer 5 are set such that the second pulse-doped layer 5 is depleted by a surface depletion layer caused by the interface state of the cap layer surface, and the surface depletion layer does not extend to the first pulse-doped layer 3. A source electrode 13, a drain electrode 16, and first and second gate electrodes 14 and 15 are formed on the semiconductor substrate surface. High-impurity-concentration ion implantation regions 10, 11, and 12 are formed at a source electrode formation region, a drain electrode formation region, and a region between the first and second gate electrode formation regions to extend from the semiconductor substrate surface to the first pulse-doped layer 3. The second electrode 15 formed on the drain electrode 16 side is sufficiently separated from the high-impurity-concentration ion implantation region 12 below the drain electrode 16.

摘要翻译： 本发明的目的是提供一种具有高漏极击穿电压和优异的高频特性的双栅极型MESFET。 本发明中使用的半导体衬底通过外延生长顺序形成非掺杂缓冲层2，杂质浓度高的薄的第一脉冲掺杂层3和下层半导体衬底1上的覆盖层7来获得。 盖层7具有夹在非掺杂层4和6之间的具有高杂质浓度的薄的第二脉冲掺杂层5.第二脉冲掺杂层5的厚度和杂质浓度被设定为使得第二脉冲掺杂 层5被由覆盖层表面的界面状态引起的表面耗尽层耗尽，并且表面耗尽层不延伸到第一脉冲掺杂层3.源电极13，漏电极16以及第一和第 第二栅电极14和15形成在半导体衬底表面上。 在源电极形成区域，漏电极形成区域以及第一和第二栅电极形成区域之间的区域形成高杂质浓度离子注入区域10,11和12，以从半导体衬底表面延伸到 第一脉冲掺杂层3.形成在漏电极16侧的第二电极15与漏电极16下方的高杂质浓度离子注入区12充分分离。

公开(公告)号：US5381157A

公开(公告)日：1995-01-10

申请号：US875015

申请日：1992-04-28

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01Q1/24 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q1/38

CPC分类号： H01Q21/0093 ,  H01Q1/247 ,  H01Q21/065

摘要： The receiving device according to this invention includes one or more patch or helical antennas and one or more receiving units formed monolithically on a single substrate. In order to widen the receiving frequency band, antenna elements are formed not directly on a compound semiconductor substrate but with a space between the antenna element and the substrate. In the patch antenna embodiment, patch elements are supported by dielectric posts, whereby there is provided a void between most of the patch antenna and the underlying semiconductor substrate.

摘要翻译： 根据本发明的接收装置包括一个或多个贴片或螺旋天线以及一个或多个接收单元，其单片地形成在单个基板上。 为了加宽接收频带，天线元件不是直接形成在复合半导体衬底上，而是在天线元件和衬底之间具有空间。 在贴片天线实施例中，贴片元件由电介质柱支撑，由此在贴片天线和下面的半导体衬底的大部分之间提供空隙。

公开(公告)号：US5164686A

公开(公告)日：1992-11-17

申请号：US791738

申请日：1991-11-15

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01L21/22 ,  H03B1/04 ,  H03B5/02 ,  H03B5/18

CPC分类号： H03B5/1876 ,  H03B2200/0028 ,  H03B2200/0058 ,  H03B2200/0088 ,  H03B2200/009 ,  H03B2202/027 ,  H03B2202/06 ,  H03B5/1852

摘要： This invention is a high-frequency oscillator including a MESFET, wherein a GaAs MESFET, in which the doping profile of an active layer has a pulse-doped structure, is used as the MESFET. Since the GaAs MESFET is formed to have the pulse-doped structure, the change in transconductance with respect to the change in gate resistance remains constant at gate voltages within a predetermined range. When the gate voltage is set to be a voltage within this predetermined range, a capacitance change with respect to a gate voltage across a gate and a source is reduced. FM noise proportional to the magnitude of this capacitance change is reduced. Accurate information transmission is not interfered with unlike in conventional arrangements.

公开(公告)号：US5070376A

公开(公告)日：1991-12-03

申请号：US631909

申请日：1990-12-21

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01L23/66 ,  H01L29/423 ,  H01L29/812 ,  H03D7/12 ,  H03K17/687

CPC分类号： H01L29/8124 ,  H01L23/66 ,  H01L29/42316 ,  H03D7/125 ,  H03K17/687 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor device includes an FET having side gate electrodes. The FET has a plurality of side gate electrodes, and the side gate electrodes, side gate input terminals and lead wires connecting them are arranged such that a difference between electrical lengths from the side gate electrodes to the input terminals (pads) is smaller than a quarter wavelength of the input signals thereto. Thus, even if a microwave signal is applied to the side gate input terminals, the signals reach the side gate electrodes with substantially the same phase and the side gate effect extends to the entire gate electrode.

摘要翻译： 半导体器件包括具有侧栅电极的FET。 FET具有多个侧栅电极，侧栅电极，侧栅极输入端和与它们连接的引线布置成使得从侧栅电极到输入端（焊盘）的电长度之间的差小于 输入信号的四分之一波长。 因此，即使微波信号施加到侧栅极输入端子，信号到达具有大致相同相位的侧栅电极，并且侧栅效应延伸到整个栅电极。

公开(公告)号：US5032885A

公开(公告)日：1991-07-16

申请号：US447059

申请日：1989-12-07

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01L27/144 ,  H01L31/105 ,  H03F3/08 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04B10/67 ,  H04B10/69

CPC分类号： H01L27/1443 ,  H01L31/105 ,  H03F3/082

摘要： In a high impedance type light receiver circuit comprising a light receiving device, an amplifier circuit for amplifying an output of the light receiving device and an equalizer for band compensation, a capacitor of the equalizer is formed by the same PN junction structure as that of the light receiving device, and the light receiving device, the amplifier circuit and the equalizer are integrated on one semiconductor substrate so that adjustment of the time constant of the equalizer is not necessary. In this manner, the productivity of a high impedance type light receiver circuit which can attain a higher sensitivity than a trans-impedance type circuit, is improved.

公开(公告)号：US4955684A

公开(公告)日：1990-09-11

申请号：US391050

申请日：1989-08-09

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： G02B6/42 ,  H01L31/0203

CPC分类号： H01L31/0203 ,  G02B6/4202

摘要： In an optical module with a substrate having an optical unit mounted thereon which substrate is provided on the bottom of a package so that the optical unit is optically coupled with an end of an optical fiber extending into the package, a chip carrier, including the optical unit, is die-bonded to a conductive land formed on the substrate. A recess is formed in the bottom of the package which faces the land. Thus, a capacitance of a parallel-plate capacitor formed by the land and the bottom of the is made negligibly small.

摘要翻译： 在具有其上安装有光学单元（3）的基板（6）的光学模块中，其设置在封装（8）的底部上，并且具有光学单元，光学单元与延伸到 封装（8），包括光学单元（3）的芯片载体（2）被芯片接合到形成在基板（6）上的导电焊盘（7）上，并且在 所述包装（8）的底部面向所述平台（7）。 因此，由平台（7）形成的并联板电容器和封装（8）的底部形成的阻止高速运转的电容可以忽略不计。