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1.发明授权公开(公告)号：US07271045B2
公开(公告)日：2007-09-18
申请号：US11240839
申请日：2005-09-30
IPC分类号： H01L21/8238
CPC分类号： H01L21/31111 , H01L29/66545 , Y10S438/926
摘要： A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
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公开(公告)号：US07166506B2
公开(公告)日：2007-01-23
申请号：US11015151
申请日：2004-12-17
IPC分类号： H01L21/8242
CPC分类号： H01L21/31053 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.
摘要翻译： 公开了一种使用至少两种材料去除步骤制造微电子结构的方法，例如在多孔开式抛光工艺中。 在一个实施例中，第一去除步骤可以是利用相对于邻接晶体管栅极的蚀刻停止层使用的层间介电层具有高选择性的浆料的化学机械抛光（CMP）步骤。 这允许第一CMP步骤在接触蚀刻停止层之后停止，这导致基本上均匀的“在晶片内”，“在晶片内”和“晶片到晶片”形态。 去除步骤可以暴露诸如晶体管栅极结构内的多晶硅栅极的临时元件。 一旦多晶硅栅极被暴露，可以采用其它工艺来产生具有期望特性的晶体管栅极。
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3.发明申请METHOD AND SYSTEM TO CONTROL POLISH RATE VARIATION INTRODUCED BY DEVICE DENSITY DIFFERENCES 审中-公开控制设备密度差异引起的波动率变化的方法和系统公开(公告)号：US20150179469A1
公开(公告)日：2015-06-25
申请号：US14137512
申请日：2013-12-20
IPC分类号： H01L21/3105 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/31055 , H01L21/7684
摘要： An embodiment includes forming a first film over first and second portions of a SOC, the first portion including a first density of structures and the second portion including a second density of structures with the first density being denser than the second density; forming a second film over the first film; polishing the second film to remove some of the second film and form (a) a first section of the second film between sections of the first film located over the first portion, and (b) a second section of the second film between sections of the second film located over the second portion; etching the first film over the first and second portions and etching the first and second sections of the second film; and polishing the first film to expose top surfaces of the structures of the first and second portions. Other embodiments are described herein.
摘要翻译： 一个实施例包括在SOC的第一和第二部分上形成第一膜，第一部分包括第一密度结构，第二部分包括具有第一密度比第二密度致密的第二密度的结构; 在第一膜上形成第二膜; 抛光所述第二膜以去除所述第二膜中的一些，并且形成（a）所述第二膜的位于所述第一部分之上的所述第一膜的部分之间的第一部分，以及（b）所述第二膜的第二部分 第二膜位于第二部分之上; 在第一和第二部分上蚀刻第一膜并蚀刻第二膜的第一和第二部分; 并抛光第一膜以暴露第一和第二部分的结构的顶表面。 本文描述了其它实施例。
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4.发明授权Polish pad with non-uniform groove depth to improve wafer polish rate uniformity 失效抛光垫具有不均匀的凹槽深度，以提高晶圆抛光速率的一致性公开(公告)号：US06951506B2
公开(公告)日：2005-10-04
申请号：US09436092
申请日：1999-11-08
申请人： Ebrahim Andideh , Matthew J. Prince
发明人： Ebrahim Andideh , Matthew J. Prince
IPC分类号： B24B1/00 , B24B7/19 , B24B37/26 , H01L21/461
CPC分类号： B24B37/26
摘要： The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.
摘要翻译： 本发明描述了一种用于在半导体晶片上产生差分抛光速率的方法。 通过定位晶片轮廓的高点和低点来确定半导体晶片的轮廓或形貌。 然后调整抛光垫的凹槽图案以优化相对于特定晶片轮廓的抛光速率。 通过增加抛光垫的凹槽图案的凹槽深度，宽度和/或密度，可以在对应于晶片轮廓的高点的区域中增加抛光速率。 通过减小抛光垫的凹槽图案的凹槽深度，宽度和/或密度，在对应于晶片轮廓的低点的区域中抛光速率可能会降低。 为了稳定晶片表面的抛光速率，为了改善抛光工艺的平坦化，可能需要这些效果的组合。
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5.发明授权Polish pad with non-uniform groove depth to improve wafer polish rate uniformity 失效抛光垫具有不均匀的凹槽深度，以提高晶圆抛光速率的一致性
公开(公告)号：US6093651A
公开(公告)日：2000-07-25
申请号：US997293
申请日：1997-12-23
申请人： Ebrahim Andideh , Matthew J. Prince
发明人： Ebrahim Andideh , Matthew J. Prince
IPC分类号： B24B1/00 , B24B7/19 , B24B37/26 , H01L21/461
CPC分类号： B24B37/26
摘要： The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.
摘要翻译： 本发明描述了一种用于在半导体晶片上产生差分抛光速率的方法。 通过定位晶片轮廓的高点和低点来确定半导体晶片的轮廓或形貌。 然后调整抛光垫的凹槽图案以优化相对于特定晶片轮廓的抛光速率。 通过增加抛光垫的凹槽图案的凹槽深度，宽度和/或密度，可以在对应于晶片轮廓的高点的区域中增加抛光速率。 通过减小抛光垫的凹槽图案的凹槽深度，宽度和/或密度，在对应于晶片轮廓的低点的区域中抛光速率可能会降低。 为了稳定晶片表面的抛光速率，为了改善抛光工艺的平坦化，可能需要这些效果的组合。
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公开(公告)号：US6083089A
公开(公告)日：2000-07-04
申请号：US909348
申请日：1997-08-11
IPC分类号： B24B37/30 , B24B37/32 , B24B49/16 , H01L21/306 , H01L21/3105 , H01L21/321 , B24B5/00
CPC分类号： H01L21/3212 , B24B37/30 , B24B37/32 , B24B49/16 , H01L21/31053
摘要： A novel method and apparatus for uniformly polishing thin films formed on a semiconductor substrate. A substrate is placed face down on a moving polishing pad so that the thin film to be polished is placed in direct contact with the moving polishing pad. The substrate is forcibly pressed against the polishing pad with pneumatic or hydraulic pressure applied to the backside of the substrate during polishing. Additionally, a wear ring is placed on the polishing pad around and adjacent to the substrate and forcibly pressed onto the polishing pad with a downward pressure from a second source so that the wear ring is coplanar with the substrate in order to eliminate edge rounding effects.
摘要翻译： 一种用于均匀研磨形成在半导体衬底上的薄膜的新方法和装置。 将基板面朝下放置在移动的抛光垫上，使得待抛光的薄膜与移动的抛光垫直接接触。 在抛光期间，基板被强制地压在抛光垫上，气压或液压施加到基板的背面。 此外，磨损环被放置在抛光垫周围并且与基底相邻并且以来自第二源的向下的压力被强制地压在抛光垫上，使得磨损环与基底共面以消除边缘圆化效应。
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公开(公告)号：US20150179785A1
公开(公告)日：2015-06-25
申请号：US14137909
申请日：2013-12-20
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/32115 , H01L21/76805 , H01L21/7684 , H01L21/76895 , H01L21/823431 , H01L21/823462 , H01L21/823475 , H01L23/49838 , H01L23/5329 , H01L23/535 , H01L24/16 , H01L27/0886 , H01L29/42372 , H01L29/4238 , H01L29/66795 , H01L29/785 , H01L2224/16227
摘要： Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了减少晶体管栅极短缺陷的技术和配置。 在一个实施例中，一种方法包括形成多条线，其中多条线中的各条线包括栅电极材料，沉积电绝缘材料以填充各线之间的区域，然后在沉积电绝缘材料之后， 至少一个独立线路的部分，以将第一晶体管器件的栅电极材料与第二晶体管器件的栅电极材料隔离。 可以描述和/或要求保护其他实施例。
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8.发明授权
公开(公告)号：US5635083A
公开(公告)日：1997-06-03
申请号：US467546
申请日：1995-06-06
IPC分类号： B24B37/30 , B24B37/32 , B24B49/16 , H01L21/306 , H01L21/3105 , H01L21/321
CPC分类号： H01L21/3212 , B24B37/30 , B24B37/32 , B24B49/16 , H01L21/31053
摘要： A novel method and apparatus for uniformly polishing thin films formed on a semiconductor substrate. A substrate is placed face down on a moving polishing pad so that the thin film to be polished is placed in direct contact with the moving polishing pad. The substrate is forcibly pressed against the polishing pad with pneumatic or hydraulic pressure applied to the backside of the substrate during polishing. Additionally, a wear ring is placed on the polishing pad around and adjacent to the substrate and forcibly pressed onto the polishing pad with a downward pressure from a second source so that the wear ring is coplanar with the substrate in order to eliminate edge rounding effects.
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公开(公告)号：US5216843A
公开(公告)日：1993-06-08
申请号：US950812
申请日：1992-09-24
IPC分类号： B24B37/26 , B24B53/007 , B24B53/017 , H01L21/304
CPC分类号： B24B53/017 , B24B37/26
摘要： An improved apparatus for polishing a thin film formed on a semiconductor substrate includes a rotatable table covered with a polishing pad. The table and the pad are then rotated relative to the substrate which is pressed down against the pad surface during the polishing process. Means is provided for generating a plurality of grooves in the pad while substrates are being polished. The continually formed grooves help to facilitate the polishing process by channeling slurry between the substrate and the pad.
摘要翻译： 用于抛光形成在半导体衬底上的薄膜的改进的设备包括被抛光垫覆盖的可旋转工作台。 然后，桌子和衬垫相对于在抛光过程中被压向衬垫表面的衬底旋转。 提供了用于在衬底被抛光时在衬垫中产生多个凹槽的装置。 连续形成的凹槽有助于通过在衬底和衬垫之间引导浆料来促进抛光过程。
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