公开(公告)号：US06913958B1

公开(公告)日：2005-07-05

申请号：US10366800

申请日：2003-02-14

申请人： Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Douglas J. Bonser

发明人： Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Douglas J. Bonser

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/84

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139

摘要： In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.

摘要翻译： 在形成半导体器件时，在用于图案化器件特征的工艺期间形成一个或多个硬掩模。 对一个或多个硬掩模进行各向同性蚀刻，以在图案化底层之前对硬掩模进行修整。 修整的硬掩模层优选为无定形碳层。

公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06764947B1

公开(公告)日：2004-07-20

申请号：US10366801

申请日：2003-02-14

申请人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

发明人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

IPC分类号： H01L214763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

摘要翻译： 在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。 应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。 应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。 在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

公开(公告)号：US06864556B1

公开(公告)日：2005-03-08

申请号：US10335445

申请日：2002-12-31

申请人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

发明人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

IPC分类号： G03F7/09 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/47 ,  H01L31/0232

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0332 ,  H01L21/28123 ,  H01L29/785

摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

公开(公告)号：US06849530B2

公开(公告)日：2005-02-01

申请号：US10334337

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L21/28123

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

公开(公告)号：US06797552B1

公开(公告)日：2004-09-28

申请号：US10299434

申请日：2002-11-19

申请人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

发明人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

摘要翻译： 使用双层硬掩模结构各向异性地图案化材料层。 在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。 在图案化材料层之后，钝化剂随后从外部源引入。 这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性 由于在不同尺寸的特征上残留的光刻胶厚度的差异。

公开(公告)号：US07268066B2

公开(公告)日：2007-09-11

申请号：US10922093

申请日：2004-08-19

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/4763

CPC分类号： H01L29/66477 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US6156658A

公开(公告)日：2000-12-05

申请号：US203774

申请日：1998-12-02

申请人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

发明人： Fei Wang ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Scott A. Bell ,  Harry J. Levinson ,  Chih Yuh Yang

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/0274 ,  H01L21/32136

摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

公开(公告)号：US06440640B1

公开(公告)日：2002-08-27

申请号：US09703092

申请日：2000-10-31

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： G03C500

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在介电层上形成过渡金属层。 在过渡金属层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到过渡金属层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的过渡金属层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，过渡金属层用作硬掩模，以通过蚀刻介电层的部分形成与通孔图案相对应的接触孔。