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65 条记录 (耗时 0.021 秒)

    Method for fabricating trench capacitors and semiconductor device with trench capacitors
    1.
    发明授权
    Method for fabricating trench capacitors and semiconductor device with trench capacitors 失效
    制造沟槽电容器的方法和具有沟槽电容器的半导体器件

    公开(公告)号：US06878600B2

    公开(公告)日：2005-04-12

    申请号：US10436426

    申请日：2003-05-12

    申请人： Albert Birner ,  Matthias Goldbach ,  Martin Franosch

    发明人： Albert Birner ,  Matthias Goldbach ,  Martin Franosch

    IPC分类号： H01L21/3063 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L27/1087

    摘要： A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.

    摘要翻译： 一种用于制造具有中孔的沟槽的沟槽电容器的方法，所述沟槽电容器适用于分立电容器和集成半导体存储器，显着增加了电容器的电极的表面积，并因此显着增加了其电容。 电化学地制造直径为约2〜50nm的小木蛾孔状通道的中孔。 因此，可以产生具有大的电容容积比的电容。 当介孔达到与另一个中孔或相邻沟槽的最小距离（自钝化）时，介孔的生长最终停止。 因此，可以以自我调节的方式避免在两个相邻介孔之间形成“短路”。 此外，提供一种半导体器件，其包括通过根据本发明的方法制造的半导体衬底的前侧上的至少一个沟槽电容器。

    Contact spring configuration for contacting a semiconductor wafer and method for producing a contact spring configuration
    2.
    发明授权
    Contact spring configuration for contacting a semiconductor wafer and method for producing a contact spring configuration 失效
    用于接触半导体晶片的接触弹簧构造和用于产生接触弹簧构造的方法

    公开(公告)号：US06903454B2

    公开(公告)日：2005-06-07

    申请号：US10324874

    申请日：2002-12-20

    申请人： Matthias Goldbach ,  Albert Birner ,  Martin Franosch

    发明人： Matthias Goldbach ,  Albert Birner ,  Martin Franosch

    IPC分类号： G01R1/067 ,  G01R1/073 ,  H01L23/48

    CPC分类号： G01R1/06727 ,  G01R1/07357 ,  G01R3/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact spring is fixed to a surface of the substrate on one side and is composed of a semiconductor material having a stress gradient which causes a permanent bending of the contact spring. The stress gradient in the semiconductor material is brought about by two semiconductor layers which are connected to one another and are mechanically strained differently. The different strains can be set by different doping or by deposition temperatures of different magnitude during the deposition of the semiconductor layers. The contact springs provide a good ohmic contact in particular with contact regions of a semiconductor wafer that are composed of a semiconductor material.

    摘要翻译： 提供了用于接触半导体晶片的接触弹簧构造。 至少一个带状接触弹簧设置在基板上。 接触弹簧在一侧固定到基板的表面，并且由具有引起接触弹簧的永久弯曲的应力梯度的半导体材料构成。 半导体材料中的应力梯度由彼此连接并且机械应变不同的两个半导体层引起。 可以通过不同的掺杂或通过在半导体层的沉积期间具有不同大小的沉积温度来设置不同的应变。 接触弹簧特别提供了由半导体材料构成的半导体晶片的接触区域的良好欧姆接触。

    Configuration and method for making contact with the back surface of a semiconductor substrate
    3.
    发明授权
    Configuration and method for making contact with the back surface of a semiconductor substrate 失效
    与半导体基板的背面接触的结构和方法

    公开(公告)号：US06863769B2

    公开(公告)日：2005-03-08

    申请号：US10661340

    申请日：2003-09-12

    申请人： Albert Birner ,  Martin Franosch ,  Matthias Goldbach ,  Volker Lehmann ,  Jörn Lützen

    发明人： Albert Birner ,  Martin Franosch ,  Matthias Goldbach ,  Volker Lehmann ,  Jörn Lützen

    IPC分类号： H01L21/00 ,  H01L21/306

    CPC分类号： H01L21/67086 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.

    摘要翻译： 设置有基体，其上设置有第一密封环和第二密封环。 基板被设置在密封环上，使得在第一密封环，第二密封环，基体和基底之间形成空腔。 可以将蚀刻物质引入到空腔中，以便对已经施加到基底上的导电层进行蚀刻。 当已经施加到基板背面的导电层未被覆盖时，可以将电解质引入空腔中，与导电层接触，从而与基板背面接触。

    Process for the simultaneous deposition of crystalline and amorphous layers with doping
    5.
    发明授权
    Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权
    用掺杂法同时沉积结晶和非晶层的工艺

    公开(公告)号：US08102052B2

    公开(公告)日：2012-01-24

    申请号：US13026326

    申请日：2011-02-14

    申请人： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

    发明人： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

    摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

    摘要翻译： 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。

    Concept for the wet-chemical removal of a sacrificial material in a material structure
    6.
    发明申请
    Concept for the wet-chemical removal of a sacrificial material in a material structure 审中-公开
    用于在材料结构中湿化学去除牺牲材料的概念

    公开(公告)号：US20060191868A1

    公开(公告)日：2006-08-31

    申请号：US11346605

    申请日：2006-02-02

    申请人： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

    发明人： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

    IPC分类号： B44C1/22 ,  H01L21/302 ,  C23F1/00

    CPC分类号： B81C1/00539 ,  B81B2203/0127

    摘要： In the inventive method for the wet-chemical removal of a sacrificial material in a material structure, there is first provided the material structure, wherein the material structure has a treatment region with the sacrificial material accessible through an opening. Subsequently, the sacrificial material is brought into contact with a wet-chemical treatment agent through the opening for the removal of the sacrificial material, wherein a mechanical vibration is generated in the wet-chemical treatment agent or in the wet-chemical treatment agent and the material structure during the contacting of the sacrificial material with the wet-chemical treatment agent.

    摘要翻译： 在用于在材料结构中湿化学去除牺牲材料的本发明的方法中，首先提供材料结构，其中材料结构具有处理区域，其中牺牲材料可通过开口接近。 随后，牺牲材料通过用于去除牺牲材料的开口与湿化学处理剂接触，其中在湿化学处理剂或湿化学处理剂中产生机械振动， 在牺牲材料与湿化学处理剂接触期间的材料结构。

    Method of producing a MOS transistor
    9.
    发明授权
    Method of producing a MOS transistor 有权
    制造MOS晶体管的方法

    公开(公告)号：US6159815A

    公开(公告)日：2000-12-12

    申请号：US269311

    申请日：1999-06-04

    申请人： Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

    发明人： Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66636 ,  H01L21/823864

    摘要： In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

    摘要翻译： PCT No.PCT / DE97 / 01933 Sec。 371日期1999年6月4日第 102（e）1999年6月4日PCT PCT 1996年9月3日PCT公布。 公开号WO98 / 13865 日期1998年4月2日为了生产具有HDD配置文件和LDD配置文件的MOS晶体管，首先在LDD配置文件的区域中形成HDD配置文件，然后是LDD配置文件，以生成陡峭的掺杂剂配置文件。 LDD分布优选通过蚀刻和原位掺杂的选择性外延生长。

    Method of operating a storage cell arrangement
    10.
    发明授权
    Method of operating a storage cell arrangement 失效
    操作存储单元布置的方法

    公开(公告)号：US6040995A

    公开(公告)日：2000-03-21

    申请号：US230614

    申请日：1999-01-28

    申请人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    发明人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    IPC分类号： H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

    CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

    摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。