公开(公告)号：US20130009312A1

公开(公告)日：2013-01-10

申请号：US13603017

申请日：2012-09-04

申请人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

发明人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

IPC分类号： H01L23/485 ,  H05K1/09 ,  H05K1/02

CPC分类号： H01L23/53295 ,  H01L21/4846 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/49894 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

摘要翻译： 微电子结构内的互连结构和用于在微电子结构内制造互连结构的方法使用可显影底部抗反射涂层和位于其上的至少一个可成像的层间电介质层，该基底包括基底电介质层和 第一导体层，其位于并形成为嵌入在所述基极介质层内。 使用可显影底部抗反射涂层和至少一个可成像的层间电介质层的事件可以通过至少一个可成像的层间间隔形成孔，例如但不限于双镶嵌孔， 介电层和可显影的抗反射涂层，以在位于和形成在第一导体层上时露出覆盖层，当在微电子结构内形成互连结构时，不使用干等离子体蚀刻方法。

公开(公告)号：US20100314768A1

公开(公告)日：2010-12-16

申请号：US12483588

申请日：2009-06-12

申请人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

发明人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/4846 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/49894 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

摘要翻译： 微电子结构内的互连结构和用于在微电子结构内制造互连结构的方法使用可显影底部抗反射涂层和位于其上的至少一个可成像的层间电介质层，该基底包括基底电介质层和 第一导体层，其位于并形成为嵌入在所述基极介质层内。 使用可显影底部抗反射涂层和至少一个可成像的层间电介质层的事件可以通过至少一个可成像的层间间隔形成孔，例如但不限于双镶嵌孔， 介电层和可显影的抗反射涂层，以在位于和形成在第一导体层上时露出覆盖层，当在微电子结构内形成互连结构时，不使用干等离子体蚀刻方法。

公开(公告)号：US08298937B2

公开(公告)日：2012-10-30

申请号：US12483588

申请日：2009-06-12

申请人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

发明人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

IPC分类号： H01L21/44

CPC分类号： H01L23/53295 ,  H01L21/4846 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/49894 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

摘要翻译： 微电子结构内的互连结构和用于在微电子结构内制造互连结构的方法使用可显影底部抗反射涂层和位于其上的至少一个可成像的层间电介质层，该基底包括基底电介质层和 第一导体层，其位于并形成为嵌入在所述基极介质层内。 使用可显影底部抗反射涂层和至少一个可成像的层间电介质层的事件可以通过至少一个可成像的层间间隔形成孔，例如但不限于双镶嵌孔， 介电层和可显影的抗反射涂层，以在位于和形成在第一导体层上时露出覆盖层，当在微电子结构内形成互连结构时，不使用干等离子体蚀刻方法。

公开(公告)号：US09059249B2

公开(公告)日：2015-06-16

申请号：US13602126

申请日：2012-09-01

申请人： Maxime Darnon ,  Qinghuang Lin

发明人： Maxime Darnon ,  Qinghuang Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L21/31 ,  H01L23/532 ,  C08G77/04

CPC分类号： H01L21/76804 ,  C08G77/04 ,  H01L21/02126 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

摘要翻译： 提供了一种互连结构，其包括直接位于衬底的表面上的至少一个图案化和固化的低k材料; 以及至少一个导电填充区域，其嵌入位于所述至少一个图案化和固化的低k材料内的互连图案内，其中所述至少一个导电填充区域在所述互连图案的下部区域具有拐点， 靠近衬底的上表面，并且互连区域具有具有基本上直的侧壁的上部区域。

公开(公告)号：US08475667B2

公开(公告)日：2013-07-02

申请号：US12820904

申请日：2010-06-22

申请人： Maxime Darnon ,  Pratik P. Joshi ,  Qinghuang Lin

发明人： Maxime Darnon ,  Pratik P. Joshi ,  Qinghuang Lin

IPC分类号： H01B13/00

CPC分类号： B82Y40/00 ,  G03F7/0046 ,  G03F7/0757 ,  G03F7/094 ,  G03F7/11 ,  Y10T428/24612

摘要： The present disclosure relates to a method of patterning a photosensitive material on a polymeric fill matrix comprising at least one latent photoacid generator; and a structure prepared according to said method. The method comprises: a. depositing a polymeric fill matrix comprising at least one latent photoacid generator; b. curing the polymeric fill matrix; c. depositing a layer of photosensitive material directly onto the cured polymeric fill matrix; and d. forming a pattern with at least one opening in the layer of photosensitive material with lithography.

摘要翻译： 本公开涉及一种在包含至少一种潜在光酸产生剂的聚合物填充基质上图案化感光材料的方法; 以及根据所述方法制备的结构。 该方法包括：a。 沉积包含至少一种潜在光酸产生剂的聚合物填充基质; b。 固化聚合物填充基质; C。 将一层感光材料直接沉积到固化的聚合物填充基质上; 和d。 通过光刻在光敏材料层中形成具有至少一个开口的图案。

公开(公告)号：US20110221062A1

公开(公告)日：2011-09-15

申请号：US12721032

申请日：2010-03-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/4821 ,  C08L83/04 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08642252B2

公开(公告)日：2014-02-04

申请号：US12721032

申请日：2010-03-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

IPC分类号： H01L21/764

CPC分类号： H01L23/4821 ,  C08L83/04 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20120280398A1

公开(公告)日：2012-11-08

申请号：US13540931

申请日：2012-07-03

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20110272810A1

公开(公告)日：2011-11-10

申请号：US12776885

申请日：2010-05-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/522 ,  G03F7/20

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08896120B2

公开(公告)日：2014-11-25

申请号：US12768267

申请日：2010-04-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/02 ,  H01L21/31 ,  H01L21/027 ,  H01L23/522

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/0276 ,  H01L21/31 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地，本文所述的方法提供了内置于可光图案化的低k材料中的互连结构，其中不同深度的气隙通过光刻图案中的低k材料中的光刻来定义。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。