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公开(公告)号:US20230387075A1
公开(公告)日:2023-11-30
申请号:US18303693
申请日:2023-04-20
Applicant: MEDIATEK INC.
Inventor: Yi-Lin TSAI , Wen-Sung HSU , Nai-Wei LIU
IPC: H01L25/065 , H01L23/538 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0655 , H01L23/5385 , H01L23/5383 , H01L23/3185 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A semiconductor package includes an interposer over a substrate that includes interconnect traces, a redistribution structure on the interposer, a first semiconductor structure, a second semiconductor structure and a third semiconductor structure on the redistribution structure. The first semiconductor structure includes a first semiconductor die and a first encapsulant that encapsulates the first semiconductor die. The second semiconductor structure includes a second semiconductor die and a second encapsulant that encapsulates the second semiconductor die. The third semiconductor structure is disposed adjacent to a corner or an edge of the substrate in a top plan view of the substrate. The third semiconductor structure includes a third semiconductor die and a third encapsulant that encapsulates the third semiconductor die. The third semiconductor structure is electrically insulated from the substrate, the first semiconductor structure and the second semiconductor structure.
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公开(公告)号:US20240153887A1
公开(公告)日:2024-05-09
申请号:US18403974
申请日:2024-01-04
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung LIN , Chia-Cheng CHANG , I-Hsuan PENG , Nai-Wei LIU
IPC: H01L23/00 , H01L23/043 , H01L23/13 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L23/562 , H01L23/043 , H01L23/13 , H01L23/3135 , H01L23/49816 , H01L23/49838 , H01L23/5383 , H01L24/16 , H01L25/0655 , H01L23/5385 , H01L2224/16227
Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.
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公开(公告)号:US20190043771A1
公开(公告)日:2019-02-07
申请号:US16002138
申请日:2018-06-07
Applicant: MEDIATEK INC.
Inventor: Chia-Cheng CHANG , Tzu-Hung LIN , I-Hsuan PENG , Nai-Wei LIU
IPC: H01L23/053 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/16 , H01L23/00
Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
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公开(公告)号:US20170098629A1
公开(公告)日:2017-04-06
申请号:US15218379
申请日:2016-07-25
Applicant: MediaTek Inc.
Inventor: Nai-Wei LIU , Tzu-Hung LIN , I-Hsuan PENG , Ching-Wen HSIAO , Wei-Che HUANG
IPC: H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L23/3114 , H01L21/568 , H01L23/3135 , H01L23/49811 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/94 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2224/94 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/19011 , H01L2924/35121 , H01L2924/37001 , H01L2224/83
Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
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公开(公告)号:US20170098589A1
公开(公告)日:2017-04-06
申请号:US15212113
申请日:2016-07-15
Applicant: MediaTek Inc.
Inventor: Nai-Wei LIU , Tzu-Hung LIN , I-Hsuan PENG , Ching-Wen HSIAO , Wei-Che HUANG
IPC: H01L23/31 , H01L23/00 , H01L23/544
CPC classification number: H01L23/544 , H01L21/561 , H01L21/568 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/29016 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/9222 , H01L2225/1035 , H01L2225/1041 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/37001
Abstract: A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.
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公开(公告)号:US20240038614A1
公开(公告)日:2024-02-01
申请号:US18342149
申请日:2023-06-27
Applicant: MEDIATEK INC.
Inventor: Yi-Lin TSAI , Nai-Wei LIU , Wen-Sung HSU
IPC: H01L23/31 , H01L25/16 , H01L23/498 , H01L23/00
CPC classification number: H01L23/3157 , H01L25/16 , H01L23/3107 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/182
Abstract: A semiconductor package structure includes a substrate, a dummy conductive mesh structure, an interposer, an underfill material, and a semiconductor die. The substrate includes a wiring structure in dielectric layers. The dummy conductive mesh structure is embedded in the substrate and is spaced apart from the wiring structure by the dielectric layers. The interposer is disposed over the substrate. The underfill material extends between the substrate and the interposer and over the dummy conductive mesh structure. The semiconductor die is disposed over the interposer and is electrically coupled to the wiring structure through the interposer.
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公开(公告)号:US20220157732A1
公开(公告)日:2022-05-19
申请号:US17515864
申请日:2021-11-01
Applicant: MEDIATEK INC.
Inventor: Yi-Lin TSAI , Nai-Wei LIU , Wen-Sung HSU
IPC: H01L23/538 , H01L23/31 , H01L23/00 , H01L25/065 , H01L25/00 , H01L21/48 , H01L21/56 , H01L21/78
Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.
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公开(公告)号:US20210175137A1
公开(公告)日:2021-06-10
申请号:US17182525
申请日:2021-02-23
Applicant: MEDIATEK INC.
Inventor: Chia-Cheng CHANG , Tzu-Hung LIN , I-Hsuan PENG , Nai-Wei LIU
IPC: H01L23/053 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/16 , H01L23/00 , H01L25/065 , H01L23/04 , H01L25/18 , H01L23/16
Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.
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公开(公告)号:US20210035930A1
公开(公告)日:2021-02-04
申请号:US16910354
申请日:2020-06-24
Applicant: MEDIATEK INC.
Inventor: Yen-Yao CHI , Nai-Wei LIU , Tzu-Hung LIN
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an antenna device and semiconductor package. The antenna device includes a conductive pattern layer including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate. The antenna device also includes a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The semiconductor package includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer. The semiconductor package also includes a first semiconductor die electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first semiconductor die.
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公开(公告)号:US20170243826A1
公开(公告)日:2017-08-24
申请号:US15418896
申请日:2017-01-30
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung LIN , I-Hsuan PENG , Ching-Wen HSIAO , Nai-Wei LIU , Wei-Che HUANG
IPC: H01L23/538 , H01L49/02 , H01L25/00 , H01L25/065 , H01L21/48 , H01L21/56 , H01L23/31 , H01L25/10
Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.
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