公开(公告)号：US11784287B2

公开(公告)日：2023-10-10

申请号：US17331306

申请日：2021-05-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Alexander Tonkikh ,  Michael Grundmann ,  Alexander Franke

IPC: H01L33/24 ,  H01L33/06 ,  H01L33/30 ,  H01L33/46

CPC classification number: H01L33/24 ,  H01L33/06 ,  H01L33/30 ,  H01L33/46

Abstract: A micro-light emitting diode includes a mesa structure that includes a first set of one or more semiconductor layers, an active layer configured to emit light, a second set of one or more semiconductor layers on the active layer, and a dielectric layer in sidewall regions of the mesa structure. A center region of the second set of one or more semiconductor layers is thicker than a sidewall region of the second set of one or more semiconductor layers, such that a distance from a surface of the sidewall region of the second set of one or more semiconductor layers to the active layer is less than a distance from a surface of the center region of the second set of one or more semiconductor layers to the active layer, thereby forming a surface potential-induced lateral potential barrier at a sidewall region of the active layer.

公开(公告)号：US11677042B2

公开(公告)日：2023-06-13

申请号：US16833614

申请日：2020-03-29

Applicant: Meta Platforms Technologies, LLC

Inventor： Markus Broell ,  Michael Grundmann ,  David Hwang ,  Stephan Lutgen ,  Brian Matthew Mcskimming ,  Anurag Tyagi

IPC: H01L33/32 ,  H01L33/00 ,  H01L27/15

CPC classification number: H01L33/0095 ,  H01L27/156 ,  H01L33/0075 ,  H01L33/32

Abstract: Disclosed herein are methods, systems, and apparatuses for an light emitting diode (LED) array apparatus. In some embodiments, the LED array apparatus may include a plurality of mesas etched from a layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, a active layer, and an N-type doped semiconductor layer. The LED array apparatus may also include one or more regrowth semiconductor layers, including a first regrowth semiconductor layer, which may be grown epitaxially over etched facets of the plurality of mesas. In some cases, for each mesa, the first regrowth semiconductor layer may overlay etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer, around an entire perimeter of the mesa.

公开(公告)号：US12125959B2

公开(公告)日：2024-10-22

申请号：US17729484

申请日：2022-04-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Daniel Henry Morris ,  John Goward ,  Chloe Astrid Marie Fabien ,  Michael Grundmann

IPC: H01L25/16 ,  G02B27/01 ,  G06F1/16 ,  G09G3/32 ,  H01L23/00 ,  H01L25/075 ,  H01L27/12 ,  H01L33/24 ,  H01L33/46 ,  H01L33/58 ,  H01L33/62

CPC classification number: H01L33/62 ,  G02B27/0172 ,  G06F1/163 ,  G09G3/32 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0753 ,  H01L25/167 ,  H01L27/1255 ,  H01L33/24 ,  H01L33/46 ,  H01L33/58 ,  G02B2027/0178 ,  G09G2310/08 ,  G09G2320/064 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display.

公开(公告)号：US11699773B2

公开(公告)日：2023-07-11

申请号：US17729524

申请日：2022-04-26

Applicant: Meta Platforms Technologies, LLC

Inventor： Chloe Astrid Marie Fabien ,  Michael Grundmann

IPC: H01L33/00 ,  H01L33/62 ,  G09G3/32 ,  H01L25/075

CPC classification number: H01L33/0095 ,  G09G3/32 ,  H01L25/0753 ,  H01L33/62 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: Disclosed herein are techniques for forming a thin-film circuit layer on an array of light-emitting diodes (LEDs). LEDs in the array of LEDs can be singulated by various processes, such as etching and ion implantation. Singulating LEDs can be performed before or after forming the thin-film circuit layer on the array of LEDs. The array of LEDs can be bonded to a transparent or non-transparent substrate.