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公开(公告)号：US07777998B2
公开(公告)日：2010-08-17
申请号：US11852396
申请日：2007-09-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译： 集成电路的电路通常包括防静电放电（ESD）事件。 除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。 除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。
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公开(公告)号：US20090067104A1
公开(公告)日：2009-03-12
申请号：US11852396
申请日：2007-09-10
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译： 集成电路的电路通常包括防静电放电（ESD）事件。 除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。 除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。
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3.发明申请DISTRIBUTION OF ELECTROSTATIC DISCHARGE (ESD) CIRCUITRY WITHIN AN INTEGRATED CIRCUIT 有权集成电路中静电放电（ESD）电路的分布公开(公告)号：US20100165522A1
公开(公告)日：2010-07-01
申请号：US12345507
申请日：2008-12-29
申请人： Michael A. Stockinger , Anthony G. Dunne , Alex P. Gerdemann , James W. Miller , Daniel J. O'Hare , Paul J. Sheridan , Jeannie Han Millaway
发明人： Michael A. Stockinger , Anthony G. Dunne , Alex P. Gerdemann , James W. Miller , Daniel J. O'Hare , Paul J. Sheridan , Jeannie Han Millaway
CPC分类号： G06F17/5068 , H01L23/60 , H01L24/14 , H01L27/0251 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.
摘要翻译： 本公开的实施例提供集成电路（IC）或半导体器件。 该半导体器件包括在半导体器件的外表面上的多个I / O焊盘或凸块，多个静电放电（ESD）保护电池和功能模块。 单独的ESD保护电池耦合到各个I / O焊盘并且位于各个I / O焊盘的下游 功能模块耦合到单个ESD保护单元的下游。 ESD保护单元保护功能模块内的电路免受静电放电事件的影响。 导轨夹可以在第一电源总线和第二电源总线之间提供ESD放电路径。 ESD保护电池可以以组形式收集以形成簇（具有线性或不规则布置图案）。 这些集群可以跨越跨越半导体器件的一个或多个功能模块或者在功能模块之间的空间或间隙中自发地分布。
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公开(公告)号：US20090294970A1
公开(公告)日：2009-12-03
申请号：US12130579
申请日：2008-05-30
IPC分类号： H01L23/538
CPC分类号： H01L23/66 , H01L23/522 , H01L23/5222 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.
摘要翻译： 集成电路包括高速电路，互连焊盘，互连焊盘下方的钝化层，第一图案化金属层和第一通孔。 高速电路用于在高速电路的端子处的高速信号。 互连焊盘位于集成电路结构的顶表面上。 第一图案化金属层在钝化层下方具有第一部分和第二部分。 第一图案化金属层的第一部分连接到高速电路的端子。 第一图案化金属层的第二部分在互连焊盘下方并且当高频信号存在于互连焊盘部分上时电浮置。 结果是降低了高速信号的电容负载，从而提高了性能。
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公开(公告)号：US08274146B2
公开(公告)日：2012-09-25
申请号：US12130579
申请日：2008-05-30
IPC分类号： H01L23/12
CPC分类号： H01L23/66 , H01L23/522 , H01L23/5222 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.
摘要翻译： 集成电路包括高速电路，互连焊盘，互连焊盘下方的钝化层，第一图案化金属层和第一通孔。 高速电路用于在高速电路的端子处的高速信号。 互连焊盘位于集成电路结构的顶表面上。 第一图案化金属层在钝化层下方具有第一部分和第二部分。 第一图案化金属层的第一部分连接到高速电路的端子。 第一图案化金属层的第二部分在互连焊盘下方并且当高频信号存在于互连焊盘部分上时电浮置。 结果是降低了高速信号的电容负载，从而提高了性能。
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公开(公告)号：US09652577B2
公开(公告)日：2017-05-16
申请号：US14505237
申请日：2014-10-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072
摘要： This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.
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7.发明申请公开(公告)号：US20160098510A1
公开(公告)日：2016-04-07
申请号：US14505237
申请日：2014-10-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072
摘要： This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.
摘要翻译： 本公开描述了创建预先标记的电路元件对象的库的方法，并且使用预先标记的电路元件对象库来设计和制造集成电路。 电路元件对象中的每一个都被“预先标记”，并且包括对电路元件对象中的每个端子具有独立的预分配电压值的嵌入式电压标记。 当电路设计者在原理图设计中插入预先标记的电路元件对象时，设计工具确定电路元件对象端子的预分配电压值中的每一个是否与它们所连接的相应网络匹配。 当电路设计人员在原理图设计中完成包括有效网络的原理图设计时，设计工具将从原理图设计生成布局设计。 当布局设计通过验证测试时，设计工具又会从布局设计中生成掩模层数据。
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公开(公告)号：US20110316610A1
公开(公告)日：2011-12-29
申请号：US12824991
申请日：2010-06-28
IPC分类号： H03K17/687 , H03K17/00
CPC分类号： H03K17/102
摘要： A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.
摘要翻译： 传输门电路包括具有第一开关装置的第一传输门，第一开关装置与第二传输门串联，具有第二开关装置，以及控制电路，其将第一传输门和第二传输门置于导通状态 提供穿过第一传输门和第二传输门的导电路径。 当第一端子的电压高于第一电压电平并且在第一和第二开关装置中的至少一个的安全工作电压区域之外时，第一开关装置保持在其安全工作电压区域内，并且第二开关装置保持在 其安全工作电压面积。
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公开(公告)号：US09293451B2
公开(公告)日：2016-03-22
申请号：US13682558
申请日：2012-11-20
CPC分类号： H01L27/0277 , H01L27/0629
摘要： An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.
摘要翻译： 集成电路电气保护装置包括半导体衬底和半导体衬底中具有第一极性的第一，第二和第三掺杂区域。 第一和第二掺杂区域通过具有第二极性的第一体区彼此分离，并且第二和第三掺杂区域通过具有第二极性的第二体区彼此分离。 第一和第二极性彼此不同。 第二极性的第四掺杂区直接邻接并与第三掺杂区接触。 在第一和第二掺杂区域之间的第一体区上形成第一栅极结构。 第二栅极结构形成在第二和第三掺杂区域之间的第二体区上。
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公开(公告)号：US09268972B2
公开(公告)日：2016-02-23
申请号：US14246132
申请日：2014-04-06
CPC分类号： G06F21/86 , G01D4/004 , G01R22/066 , H04Q9/14
摘要： A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
摘要翻译： 篡改检测器具有通过篡改检测接口连接到篡改检测端口的篡改检测逻辑。 实时时钟（RTC）提供时钟信号并具有电池。 处理器由处于供电操作模式的外部电源供电并具有断电模式。 在唤醒配置中，特定I / O端口上的唤醒信号会从断电模式唤醒外部电源，以便在电池电源不可用时向RTC和篡改检测接口供电。 篡改检测端口在电池没有ESD问题的情况下即使卸下或放电也能继续工作。 特定的I / O端口可以被配置为被动篡改检测。
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