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1.发明申请DISTRIBUTION OF ELECTROSTATIC DISCHARGE (ESD) CIRCUITRY WITHIN AN INTEGRATED CIRCUIT 有权集成电路中静电放电（ESD）电路的分布公开(公告)号：US20100165522A1
公开(公告)日：2010-07-01
申请号：US12345507
申请日：2008-12-29
申请人： Michael A. Stockinger , Anthony G. Dunne , Alex P. Gerdemann , James W. Miller , Daniel J. O'Hare , Paul J. Sheridan , Jeannie Han Millaway
发明人： Michael A. Stockinger , Anthony G. Dunne , Alex P. Gerdemann , James W. Miller , Daniel J. O'Hare , Paul J. Sheridan , Jeannie Han Millaway
CPC分类号： G06F17/5068 , H01L23/60 , H01L24/14 , H01L27/0251 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Embodiments of the present disclosure provide an integrated circuit (IC) or semiconductor device. This semiconductor device includes a number of I/O pads or bumps on an outer surface of the semiconductor device, a number of electrostatic discharge (ESD) protection cells and functional modules. Individual ESD protection cells couple to and are downstream of individual I/O pads. Functional modules coupled to and are downstream of individual ESD protection cells. The ESD protection cells protect circuitry within the functional module from electrostatic discharge events. A rail clamp may provide an ESD discharge path between a first power supply bus and a second power supply bus. The ESD protection cells may be collected in groups to form clusters (with linear or irregular placement patterns). These clusters may be distributed autarchically across the semiconductor device overlapping one or more functional modules or within spaces or gaps between the functional modules.
摘要翻译： 本公开的实施例提供集成电路（IC）或半导体器件。 该半导体器件包括在半导体器件的外表面上的多个I / O焊盘或凸块，多个静电放电（ESD）保护电池和功能模块。 单独的ESD保护电池耦合到各个I / O焊盘并且位于各个I / O焊盘的下游 功能模块耦合到单个ESD保护单元的下游。 ESD保护单元保护功能模块内的电路免受静电放电事件的影响。 导轨夹可以在第一电源总线和第二电源总线之间提供ESD放电路径。 ESD保护电池可以以组形式收集以形成簇（具有线性或不规则布置图案）。 这些集群可以跨越跨越半导体器件的一个或多个功能模块或者在功能模块之间的空间或间隙中自发地分布。
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公开(公告)号：US09478529B2
公开(公告)日：2016-10-25
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理地连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
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公开(公告)号：US20150349522A1
公开(公告)日：2015-12-03
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译： 集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。 多个I / O单元的第一组沿着集成电路的管芯边缘布置。 多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。 对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分 第一组和第二组的邻接I / O单元。 集成电路包括ESD钳位和触发电路。
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公开(公告)号：US20090294970A1
公开(公告)日：2009-12-03
申请号：US12130579
申请日：2008-05-30
IPC分类号： H01L23/538
CPC分类号： H01L23/66 , H01L23/522 , H01L23/5222 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.
摘要翻译： 集成电路包括高速电路，互连焊盘，互连焊盘下方的钝化层，第一图案化金属层和第一通孔。 高速电路用于在高速电路的端子处的高速信号。 互连焊盘位于集成电路结构的顶表面上。 第一图案化金属层在钝化层下方具有第一部分和第二部分。 第一图案化金属层的第一部分连接到高速电路的端子。 第一图案化金属层的第二部分在互连焊盘下方并且当高频信号存在于互连焊盘部分上时电浮置。 结果是降低了高速信号的电容负载，从而提高了性能。
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公开(公告)号：US07777998B2
公开(公告)日：2010-08-17
申请号：US11852396
申请日：2007-09-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译： 集成电路的电路通常包括防静电放电（ESD）事件。 除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。 除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。
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公开(公告)号：US08274146B2
公开(公告)日：2012-09-25
申请号：US12130579
申请日：2008-05-30
IPC分类号： H01L23/12
CPC分类号： H01L23/66 , H01L23/522 , H01L23/5222 , H01L23/60 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.
摘要翻译： 集成电路包括高速电路，互连焊盘，互连焊盘下方的钝化层，第一图案化金属层和第一通孔。 高速电路用于在高速电路的端子处的高速信号。 互连焊盘位于集成电路结构的顶表面上。 第一图案化金属层在钝化层下方具有第一部分和第二部分。 第一图案化金属层的第一部分连接到高速电路的端子。 第一图案化金属层的第二部分在互连焊盘下方并且当高频信号存在于互连焊盘部分上时电浮置。 结果是降低了高速信号的电容负载，从而提高了性能。
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公开(公告)号：US20090067104A1
公开(公告)日：2009-03-12
申请号：US11852396
申请日：2007-09-10
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译： 集成电路的电路通常包括防静电放电（ESD）事件。 除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。 除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。
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公开(公告)号：US08129226B2
公开(公告)日：2012-03-06
申请号：US12599625
申请日：2007-05-10
IPC分类号： H01L21/44
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/4951 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48471 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/85191 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/4554
摘要： A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
摘要翻译： 形成诸如球栅阵列封装的封装组件（30），其通过使用设置在模具（52）上的封装的图案化引线框导体（59）来分布跨集成电路管芯（52）的内部区域的电力 ）并且接合到形成在BGA载体衬底（42）中的多个接合焊盘（45）和内部管芯区域中，从而将内部管芯区域电连接到外部提供的参考电压。
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公开(公告)号：US20110020133A1
公开(公告)日：2011-01-27
申请号：US12897048
申请日：2010-10-04
申请人： James W. Miller
发明人： James W. Miller
IPC分类号： F03D1/00
CPC分类号： F03D1/0658 , F03D1/0608 , F05B2240/30 , Y02E10/721 , Y02E10/726
摘要： A pair of airfoil blades having a longitudinal axis coincident with one another. Each blade is bent at the center on the plane of the chord. Each blade has an airfoil tip blade placed at the outer most trailing edge. The blades are affixed by their root ends to opposite ends of a torsion shaft. The blade chords are offset from one another, which defines a blade pitch angle. The torsion shaft is journaled perpendicular through a driveshaft, whereas the rotation of the blades can transfer through the torsion shaft to the driveshaft and cause the driveshaft to turn, eliminating the need for a hub. The blades are adapted to pivot along with the torsion shaft. The blades lie in substantially the same plane, and are adapted for rotation in a plane orthogonal to the longitudinal axis of the driveshaft. Each blade has an airfoil shaped fluid gate valve disposed on the leading edge.
摘要翻译： 一对具有彼此重合的纵轴的翼型叶片。 每个叶片在和弦平面上的中心弯曲。 每个叶片具有放置在最外侧最后缘的翼型末端叶片。 叶片的根端固定在扭转轴的相对端。 叶片和弦彼此偏移，这限定了叶片桨距角。 扭转轴通过驱动轴垂直地轴向旋转，而叶片的旋转可以通过扭转轴传递到驱动轴，并使驱动轴转动，从而无需轮毂。 叶片适于与扭转轴一起枢转。 叶片位于基本上相同的平面中，并且适于在与驱动轴的纵向轴线正交的平面中旋转。 每个叶片具有设置在前缘上的翼型流体闸阀。
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公开(公告)号：US07817387B2
公开(公告)日：2010-10-19
申请号：US11971591
申请日：2008-01-09
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
摘要翻译： 静电放电（ESD）保护电路耦合到电源电压轨，并包括多个独立的栅极场效应晶体管（MIGFET），预驱动器和热门偏置电路。 MIGFET具有耦合在输出焊盘和电源电压轨之间的源/漏路径，并且具有第一栅极端子和第二栅极端子。 预驱动电路有一个输出。 热门偏置电路耦合到MIGFET的第一栅极端子，并且预驱动器电路的输出耦合到MIGFET的第二栅极端子。 热门偏置电路被配置为在ESD事件期间向MIGFET的第一栅极端施加偏置电压，这增加了MIGFET的击穿电压，以便更好地承受ESD事件。
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