摘要:
A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.
摘要:
A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.
摘要:
Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.
摘要:
Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.
摘要:
A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.
摘要:
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要:
Technologies for secure offline activation of hardware features include a target computing device having a platform controller hub (PCH) including a converged security and manageability engine (CSME) and a number of in-field programmable fuses (IFPs). During assembly of the target computing device by an original equipment manufacturer (OEM), the CSME is provided a list of hardware features to be activated. The CSME configures the IFPs to enable the requested features, generates a digital receipt including the activated features and a unique device ID, and signs the receipt using a unique device key. Signed receipts may be periodically submitted to a vendor computing device, which verifies the signed receipts, extracts the active feature list, and bills the OEM for activated features of the PCHs. The vendor computing device may bill the OEM a maximum price for PCHs for which there is no associated signed receipt. Other embodiments are described and claimed.
摘要:
Embodiments include monitoring a computing system to determine whether firmware of the computing system is corrupted, hung up, or requires automatic update. The computing system may then request firmware update data over a network. Moreover, the computing system may include a controller with capability to determine whether the firmware is corrupted or hung and request and receive firmware update data over a network. In addition, the controller may have the capability operate when the firmware is corrupted or hung up, if the processor is held up, and if the operating system is halted, hung up, or soft-off. In addition, if the controller detects that the firmware is corrupted or hung up, the controller may halt the processor while updating the firmware.
摘要:
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要:
Embodiments include monitoring a computing system to determine whether firmware of the computing system is corrupted, hung up, or requires automatic update. The computing system may then request firmware update data over a network. Moreover, the computing system may include a controller with capability to determine whether the firmware is corrupted or hung and request and receive firmware update data over a network. In addition, the controller may have the capability operate when the firmware is corrupted or hung up, if the processor is held up, and if the operating system is halted, hung up, or soft-off. In addition, if the controller detects that the firmware is corrupted or hung up, the controller may halt the processor while updating the firmware.