利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.027 秒)

    Apparatus for adapting a rocket-assisted projectile for launch from a smooth bore tube
    2.
    发明授权
    Apparatus for adapting a rocket-assisted projectile for launch from a smooth bore tube 有权
    用于使火箭辅助的弹丸用于从光滑的钻孔管发射的装置

    公开(公告)号：US08434394B1

    公开(公告)日：2013-05-07

    申请号：US12580412

    申请日：2009-10-16

    申请人： Gregory Malejko ,  Daniel Pascua ,  Peter Burke ,  Keith Fulton

    发明人： Gregory Malejko ,  Daniel Pascua ,  Peter Burke ,  Keith Fulton

    IPC分类号： F41F3/00 ,  F42B15/00

    CPC分类号： F42B14/06 ,  F42B10/14 ,  F42B15/105 ,  F42B15/36

    摘要： An apparatus for adapting a rocket-assisted artillery projectile of a first caliber for firing from a smooth bore tube of a second caliber may include an adapter for connecting to an aft end of the rocket-assisted artillery projectile. The adapter may include a main channel for receiving rocket exhaust, a plurality of sub-channels that lead from the main channel to an exterior of the adapter, and an ignition channel that leads from the main channel to an ignition delay disposed in the adapter. A tail boom may be fixed to an aft end of the adapter. The tail boom may include an opening in a fore end that communicates with the ignition delay in the adapter. Lifting surfaces, such as fins, may be attached to the tail boom.

    摘要翻译： 用于使来自第二口径的光滑钻孔管的第一口径的火箭辅助炮弹的适配装置可以包括用于连接到火箭辅助炮弹的后端的适配器。 适配器可以包括用于接收火箭排气的主通道，从主通道引导到适配器的外部的多个子通道以及从主通道引导到设置在适配器中的点火延迟的点火通道。 尾杆可以固定到适配器的后端。 尾杆可以包括与适配器中的点火延迟相通的前端开口。 提升表面，例如翅片，可附接到尾部吊杆。

    Direct Smelting Plant and Process
    3.
    发明申请
    Direct Smelting Plant and Process 有权
    直接冶炼厂和工艺

    公开(公告)号：US20070272058A1

    公开(公告)日：2007-11-29

    申请号：US10576852

    申请日：2004-10-16

    申请人： Andreas Orth ,  David Leigh ,  Peter Burke

    发明人： Andreas Orth ,  David Leigh ,  Peter Burke

    IPC分类号： C21B15/00 ,  C22B3/02

    CPC分类号： F27B3/18 ,  C21B5/023 ,  C21B13/00 ,  C21B13/0013 ,  C21B13/143 ,  C21C5/567 ,  F27D13/00 ,  Y02P10/216

    摘要： The present invention relates to a direct smelting plant and a direct smelting process for producing molten metal from a metalliferous feed material, such as ores, partly reduced ores, and metal-containing waste streams, the latter of which comprising the steps of (a) pretreating metalliferous feed material in a pretreatment unit and producing pretreated feed material having a temperature of at least 200° C., (b) storing pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material storage means, (c) transferring pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material transfer line to a solids delivery means of a direct smelting vessel, and (d) delivering pretreated metalliferous feed material into the direct smelting vessel and smelting metalliferous feed material to molten metal in the vessel.

    摘要翻译： 本发明涉及一种直接熔炼设备和用于从含金属的原料如矿石，部分还原的矿石和含金属的废物流中生产熔融金属的直接熔炼方法，后者包括以下步骤：（a） 在预处理单元中预处理含金属进料，并生产温度至少为200℃的预处理进料;（b）在热进料材料储存器中储存温度至少为200℃的预处理含金属进料 是指（c）在热进料输送管线中将压力为至少200℃的预处理的含金属进料传送到直接熔炼容器的固体输送装置，以及（d）将预处理的含金属进料输送到 直接熔炼容器和冶炼含金属进料到容器中的熔融金属。

    Method for fabricating planar semiconductor wafers
    5.
    发明授权
    Method for fabricating planar semiconductor wafers 有权
    制造平面半导体晶圆的方法

    公开(公告)号：US07179736B2

    公开(公告)日：2007-02-20

    申请号：US10966074

    申请日：2004-10-14

    申请人： Byung-Sung Leo Kwak ,  Peter Burke ,  Sey-Shing Sun

    发明人： Byung-Sung Leo Kwak ,  Peter Burke ,  Sey-Shing Sun

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/7684

    摘要： The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.

    摘要翻译： 本发明涉及一种制造平面半导体晶片的方法。 该方法包括在半导体晶片表面上形成电介质层，该半导体晶片表面具有通孔，沟槽和平面区域。 然后在电介质层上形成阻挡层和种子金属层。 晶片是包含加速器的镀液中的下一个位置，该加速器倾向于在通路和沟槽中收集，以加速相对于晶片的平面区域在这些区域中的电镀速率。 达到间隙填充点后，通过去除晶片上的电镀偏压来停止电镀。 然后在该过程中引入平衡时段，允许较高浓度的促进剂添加剂和浴中的其它组分）]在通孔和沟槽区域上方在电镀浴中平衡。 平衡后恢复晶片上的块体电镀。 因此避免了在通孔和沟槽区域上的晶片上的过电镀，导致晶片上更平面的金属化层，而不使用不利地影响间隙填充能力的矫直添加剂。

    Self-aligned cell integration scheme
    6.
    发明申请
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号：US20060281256A1

    公开(公告)日：2006-12-14

    申请号：US11312849

    申请日：2005-12-20

    申请人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    发明人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    IPC分类号： H01L21/336

    CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

    摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

    Filter assembly for a reprocessor
    7.
    发明申请
    Filter assembly for a reprocessor 有权
    用于再处理器的过滤组件

    公开(公告)号：US20050025663A1

    公开(公告)日：2005-02-03

    申请号：US10633343

    申请日：2003-08-01

    申请人： Peter Burke ,  Karl Ludwig ,  Jude Kral ,  Francis Zelina

    发明人： Peter Burke ,  Karl Ludwig ,  Jude Kral ,  Francis Zelina

    IPC分类号： A61L2/02 ,  A61L2/16 ,  A61L2/18 ,  C02F1/44 ,  C02F1/50 ,  C02F1/68 ,  C02F1/72 ,  C02F9/00 ,  A61L2/00

    CPC分类号： C02F1/444 ,  A61L2/022 ,  A61L2/16 ,  A61L2/18 ,  C02F1/001 ,  C02F1/32 ,  C02F1/44 ,  C02F1/50 ,  C02F1/688 ,  C02F1/722 ,  C02F9/00 ,  C02F2301/08

    摘要： A reprocessor having a circulation system for circulating a microbial deactivation fluid through a chamber that forms a part of the circulation system. The reprocessor includes a water filtration system for filtering water used in the reprocessor. The water filtration system includes a fluid feed line connectable to a source of pressurized water. A first filter and second filter elements are disposed in the fluid feed line for filtering fluids flowing therethrough. The second filter element is downstream from the first filter element and has the capacity to filter particles smaller than the first filter element. The fluid feed line forms a fluid path for water entering the reprocessor, and defines a portion of a path for microbial deactivation fluid circulated through the circulation system.

    摘要翻译： 一种具有循环系统的再处理器，用于使微生物灭活流体循环通过形成循环系统的一部分的室。 再处理器包括用于过滤重新处理器中使用的水的过滤系统。 水过滤系统包括可连接到加压水源的流体供给管线。 第一过滤器和第二过滤器元件设置在流体供给管线中，用于过滤流过其中的流体。 第二过滤元件在第一过滤器元件的下游，并且具有过滤小于第一过滤元件的颗粒的能力。 流体供给管路形成用于进入再处理器的水的流体路径，并且限定通过循环系统循环的微生物去活化流体的路径的一部分。

    Device and method for mitochondrial membrane potential assessment
    8.
    发明授权
    Device and method for mitochondrial membrane potential assessment 有权
    线粒体膜电位评估装置及方法

    公开(公告)号：US08961759B2

    公开(公告)日：2015-02-24

    申请号：US13412515

    申请日：2012-03-05

    申请人： Peter Burke ,  Tae-Sun Lim ,  Antonio Davila ,  Douglas C. Wallace ,  Katayoun Zand

    发明人： Peter Burke ,  Tae-Sun Lim ,  Antonio Davila ,  Douglas C. Wallace ,  Katayoun Zand

    IPC分类号： G01N27/414 ,  G01N27/403 ,  G01N33/483

    CPC分类号： G01N27/4035 ,  G01N33/4833 ,  Y10S435/82

    摘要： A microfluidic sensor device includes a substrate having patterned thereon at least one Ag/AgCl electrode (working electrode) and an inner chamber overlying the at least one Ag/AgCl electrode. The device includes an ion selective permeable membrane permeable to TPP+ disposed on one side of the first chamber and a sensing chamber overlying the ion selective permeable membrane. A separate reference electrode is inserted into the sensing chamber. The working electrode and reference electrode are coupled to a voltmeter to measure voltage. This voltage can then be translated into a TPP+ concentration which is used to determine the mitochondrial membrane potential (ΔΨm).

    摘要翻译： 微流体传感器装置包括其上具有图案化的至少一个Ag / AgCl电极（工作电极）和覆盖至少一个Ag / AgCl电极的内室的基板。 该装置包括设置在第一室的一侧上的可渗透TPP +的离子选择性渗透膜和覆盖离子选择性渗透膜的感测室。 单独的参考电极插入感测室。 工作电极和参考电极耦合到电压表以测量电压。 然后可以将该电压转化为用于确定线粒体膜电位（＆Dgr;Ψm）的TPP +浓度。

    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
    10.
    发明申请
    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 失效
    用于增加铜互连结构中电磁寿命的电介质障碍层

    公开(公告)号：US20070190784A1

    公开(公告)日：2007-08-16

    申请号：US11736402

    申请日：2007-04-17

    申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

    发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

    摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

    摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。